#include "sandpoint_serial.h"
+#include "sandpoint.h"
+
+//#define SYS_266 1
+#define SYS_200 1
+//#define SYS_166 1
+
+//REX:
+#if 0
extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
extern int pckbd_getkeycode(unsigned int scancode);
extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
extern void pckbd_leds(unsigned char leds);
extern void pckbd_init_hw(void);
extern unsigned char pckbd_sysrq_xlate[128];
+#endif
extern void gen550_progress(char *, unsigned short);
extern void gen550_init(int, struct serial_struct *);
static void sandpoint_halt(void);
+#ifdef CONFIG_SERIAL_TEXT_DEBUG
+#include <linux/serial.h>
+#include <linux/serialP.h>
+#include <linux/serial_reg.h>
+#include <asm/serial.h>
+
+static struct serial_state rs_table[RS_TABLE_SIZE] = {
+ SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
+};
+
+#endif
+
/*
* Define all of the IRQ senses and polarities. Taken from the
* Sandpoint X3 User's manual.
*/
static u_char sandpoint_openpic_initsenses[] __initdata = {
+// REX
+#if 0
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 0: SIOINT */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 2: PCI Slot 1 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 3: PCI Slot 2 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 5: PCI Slot 4 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 8: IDE (INT C) */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* 9: IDE (INT D) */
+#else
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 17, EPIC IRQ 1 - PCI1 - flash*/
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 18, EPIC IRQ 2 - LAN*/
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 19, EPIC IRQ 3 - Not used*/
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 20, EPIC IRQ 4 - Not used*/
+ 1
+#endif
};
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
+// REX
+#if 0
{
{16, 0, 0, 0}, /* IDSEL 11 - i8259 on Windbond */
{ 0, 0, 0, 0}, /* IDSEL 12 - unused */
};
const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
+#else
+ {
+ { 0, 0, 0, 0 }, /* IDSEL 13 - mini-PCI */
+ { 1, -1, 2, 0 }, /* IDSEL 14 - NEC USB2.0 */
+ { 3, 0, 0, 0 }, /* IDSEL 15 - ADM983 */
+ { 4, 0, 0, 0 }
+ };
+
+ const long min_idsel = 13, max_idsel = 16, irqs_per_slot = 4;
+#endif
return PCI_IRQ_TABLE_LOOKUP;
}
+#if 0 //REX
static void __init
sandpoint_setup_winbond_83553(struct pci_controller *hose)
{
*/
early_write_config_dword(hose, 0, devfn, 0x40, 0x00ff0011);
}
+#endif
+
+#ifndef CONFIG_SANDPOINT_X3
+/* On the sandpoint X2, we must avoid sending configuration cycles to
+ * device #12 (IDSEL addr = AD12).
+ */
+static int
+sandpoint_exclude_device(u_char bus, u_char devfn)
+{
+#if 0
+ if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ else
+ return PCIBIOS_SUCCESSFUL;
+#endif
+#ifdef REX_DBG_PCI
+ printk("REX_DBG_PCI: dev-fun is %X:%X.\n",PCI_SLOT(devfn), PCI_FUNC(devfn));
+#endif
+ if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
+ {
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+ else
+ {
+ return PCIBIOS_SUCCESSFUL;
+ }
+
+}
+#endif
static void __init
sandpoint_find_bridges(void)
hose->first_busno = 0;
hose->last_busno = 0xff;
+//REX
+#if 0
if (mpc10x_bridge_init(hose,
MPC10X_MEM_MAP_B,
MPC10X_MEM_MAP_B, MPC10X_MAPB_EUMB_BASE) == 0) {
+#endif
+ if (mpc10x_bridge_init(hose,
+ MPC10X_MEM_MAP_B,
+ MPC10X_MEM_MAP_B,
+ 0xfc000000) == 0) {
/* Do early winbond init, then scan PCI bus */
- sandpoint_setup_winbond_83553(hose);
+ //sandpoint_setup_winbond_83553(hose);
+#ifndef CONFIG_SANDPOINT_X3
+ ppc_md.pci_exclude_device = sandpoint_exclude_device;
+#endif
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = NULL;
}
#endif
}
-
+#if 0 //REX:
#define SANDPOINT_87308_CFG_ADDR 0x15c
#define SANDPOINT_87308_CFG_DATA 0x15d
return;
}
+#endif //REX:
static void __init
sandpoint_init2(void)
{
/* Do Sandpoint board specific initialization. */
+#if 0
sandpoint_fix_winbond_83553();
sandpoint_setup_natl_87308();
request_region(0x80, 0x10, "dma page reg");
request_region(0xa0, 0x20, "pic2");
request_region(0xc0, 0x20, "dma2");
-
+#endif //REX:
return;
}
* as offsets starting at 0x50200, we need to adjust occordinly.
*/
+#if 1
+#ifdef CONFIG_SANDPOINT_X3
+//REX
/* Map serial interrupt 0 */
openpic_set_sources(0, 1, OpenPIC_Addr + 0x10200);
/* Map serial interrupts 2-5 */
/* Skip reserved space and map Message Unit Interrupt (I2O) */
openpic_set_sources(10, 1, OpenPIC_Addr + 0x110C0);
- openpic_init(NUM_8259_INTERRUPTS);
- /* The cascade is on EPIC IRQ 0 (Linux IRQ 16). */
- openpic_hookup_cascade(16, "8259 cascade to EPIC", &i8259_irq);
+ openpic_set_sources(0, 138, NULL);
+#else
+ /* Map EPIC IRQs 0-3 */
+ openpic_set_sources(0, 5, OpenPIC_Addr + 0x10200);
+ /* Skip reserved space and map i2c and DMA Ch[01] */
+ openpic_set_sources(113, 3, OpenPIC_Addr + 0x11020);
+ /* Skip reserved space and map Message Unit Interrupt (I2O) */
+ openpic_set_sources(118, 1, OpenPIC_Addr + 0x110C0);
+ //REX: UART
+ openpic_set_sources(121, 1, OpenPIC_Addr + 0x11120); //ttyS0
+
+ openpic_set_sources(122, 1, OpenPIC_Addr + 0x11140); //ttyS1 jackl
+#endif
+#endif
+#if 1 //REX:
+#if 0//by Musenki, cause it will panic!
+ openpic_set_sources(0, 32, NULL);
+ openpic_set_sources(129, 3, NULL);//I2C
+ openpic_set_sources(134, 1, NULL);//Mesg
+ openpic_set_sources(137, 2, NULL);//DUART
+#endif
+ //openpic_init(1, 0, 0, -1);
+ openpic_init(0);
+ /* The cascade is either on EPIC IRQ 1 or 2 on an X2 or on X3 it's
+ * on EPIC IRQ 0.
+ */
+ //openpic_hookup_cascade(SANDPOINT_SIO_IRQ, "8259 cascade to EPIC",
+ // &i8259_irq);
/*
* openpic_init() has set up irq_desc[0-23] to be openpic
* interrupts. We need to set irq_desc[0-15] to be 8259 interrupts.
* We then need to request and enable the 8259 irq.
*/
- for (i = 0; i < NUM_8259_INTERRUPTS; i++)
- irq_desc[i].handler = &i8259_pic;
+ //for (i = 0; i < NUM_8259_INTERRUPTS; i++)
+ // irq_desc[i].handler = &i8259_pic;
/*
* The EPIC allows for a read in the range of 0xFEF00000 ->
* 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
*/
- i8259_init(0xfef00000);
+ //i8259_init(0xfef00000);
+#endif //REX:
}
+/*
+ * Because the Sandpoint X2 has the i8259 cascade sharing an IRQ with a
+ * PCI device, if we have a possible cascade IRQ we need to see if the
+ * i8259 has something pending. The only issue here is that the cascade
+ * IRQs will get a higher priority than an OpenPIC one, but this should be
+ * OK.
+ */
+static int
+sandpoint_get_irq(struct pt_regs *regs)
+{
+ int irq, cascade_irq;
+
+ irq = openpic_irq();
+ //REX:
+#if 0
+ if ((irq != 127)&&(irq != 2)&&(irq!=121))
+ printk("sandpoint_get_irq: irq = %d\n", irq);
+#endif
+ //if (irq == SANDPOINT_SIO_IRQ)
+ //REX:
+ if (0)
+ {
+ cascade_irq = i8259_irq(regs);
+
+ if (cascade_irq != -1) {
+ irq = cascade_irq;
+ openpic_eoi();
+ }
+ } else if (irq == OPENPIC_VEC_SPURIOUS)
+ irq = -1;
+
+ return irq;
+}
+//REX:
+#if 0
static u32
sandpoint_irq_cannonicalize(u32 irq)
{
else
return irq;
}
+#endif
static unsigned long __init
sandpoint_find_end_of_memory(void)
bd_t *bp = (bd_t *) __res;
if (bp->bi_memsize)
+ {
+ //REX:
+ printk("Total memory %d MB.\n", bp->bi_memsize);
return bp->bi_memsize;
+ }
/* This might be fixed in DINK32 12.4, or we'll have another
* way to determine the correct memory size anyhow. */
static void __init
sandpoint_map_io(void)
{
- io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
+ io_block_mapping(0xfc000000, 0xfc000000, 0x04000000, _PAGE_IO);
+ //REX:
+ //rs_table[0].iomem_base = ioremap_base - 0x100000 + 0x4500;
}
+/*
+ * Due to Sandpoint X2 errata, the Port 92 will not work.
+ */
static void
sandpoint_restart(char *cmd)
{
- __cli();
+ ulong msr, addr;
+ //printk("Jumping to start address...\n");
+ __cli();
+//REX:
+#if 1
/* Set exception prefix high - to the firmware */
_nmask_and_or_msr(0, MSR_IP);
/* Reset system via Port 92 */
- outb(0x00, 0x92);
- outb(0x01, 0x92);
+ //outb(0x00, 0x92);
+ //outb(0x01, 0x92);
+#endif
+
+ /* Interrupts and MMU off */
+ __asm__ ("mtspr 81, 0");
+
+ /* Interrupts and MMU off */
+ __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
+
+ msr &= ~0x1030;
+ __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+ /*
+ * * Trying to execute the next instruction at a non-existing address
+ * * should cause a machine check, resulting in reset
+ **/
+ addr = 0xFFF00100;
+ ((void (*)(void)) addr) ();
for (;;) ; /* Spin until reset happens */
}
return 0;
}
-
+#if 0 //REX:
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
/*
* IDE support.
return;
}
#endif
+#endif //REX:
/*
* Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
static __inline__ void
sandpoint_set_bat(void)
{
-#if 1
+//REX:
+#if 0
mb();
mtspr(DBAT1U, 0xf8000ffe);
mtspr(DBAT1L, 0xf800002a);
mb();
-#else
unsigned long bat3u, bat3l;
__asm__ __volatile__(" lis %0,0xf800\n \
isync\n \
sync ":"=r"(bat3u), "=r"(bat3l));
#endif
+ unsigned long bat3u, bat3l;
+
+ __asm__ __volatile__(
+ " lis %0,0xf000\n \
+ ori %1,%0,0x002a\n \
+ ori %0,%0,0x1fff\n \
+ mtspr 0x21e,%0\n \
+ mtspr 0x21f,%1\n \
+ isync\n \
+ sync "
+ : "=r" (bat3u), "=r" (bat3l));
+
+
}
+#ifdef CONFIG_SERIAL_TEXT_DEBUG
+#include <linux/serial.h>
+#include <linux/serialP.h>
+#include <linux/serial_reg.h>
+#include <asm/serial.h>
+
+
+volatile unsigned char *com_port;
+volatile unsigned char *com_port_lsr;
+
+static void
+serial_writechar(char c)
+{
+ while ((*com_port_lsr & UART_LSR_THRE) == 0)
+ ;
+ *com_port = c;
+}
+
+void
+sandpoint_progress(char *s, unsigned short hex)
+{
+ volatile char c;
+
+ //jackl
+ com_port = (volatile unsigned char *) rs_table[0].port;
+ //com_port = (volatile unsigned char *) rs_table[1].port; //jackl
+ com_port_lsr = com_port + UART_LSR;
+
+ while ((c = *s++) != 0)
+ serial_writechar(c);
+
+ /* Most messages don't have a newline in them */
+ serial_writechar('\n');
+ serial_writechar('\r');
+}
+#endif /* CONFIG_SERIAL_TEXT_DEBUG */
+//REX:
+void calibrate_decr() {
+ int freq, divisor;
+
+ //jackl system_clock
+ #ifdef SYS_266
+ freq = 133000000;
+ #endif
+ #ifdef SYS_200
+ freq = 100000000;
+ #endif
+ #ifdef SYS_166
+ freq = 66000000;
+ #endif
+ //REX: to avoid slow time!
+ divisor = 4;
+ tb_ticks_per_jiffy = freq / HZ / divisor;
+ tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
+}
TODC_ALLOC();
void __init
/* Map in board regs, etc. */
sandpoint_set_bat();
-
+//REX:
+#if 0
isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
ISA_DMA_THRESHOLD = 0x00ffffff;
DMA_MODE_READ = 0x44;
DMA_MODE_WRITE = 0x48;
-
+#endif
ppc_md.setup_arch = sandpoint_setup_arch;
ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
- ppc_md.irq_cannonicalize = sandpoint_irq_cannonicalize;
+ //ppc_md.irq_cannonicalize = sandpoint_irq_cannonicalize;
ppc_md.init_IRQ = sandpoint_init_IRQ;
- ppc_md.get_irq = openpic_get_irq;
+ //ppc_md.get_irq = openpic_get_irq;
+ ppc_md.get_irq = sandpoint_get_irq;
ppc_md.init = sandpoint_init2;
ppc_md.restart = sandpoint_restart;
ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
ppc_md.setup_io_mappings = sandpoint_map_io;
-
+ ppc_md.calibrate_decr = calibrate_decr;
+#ifdef REX_TODC
TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.nvram_read_val = todc_mc146818_read_val;
ppc_md.nvram_write_val = todc_mc146818_write_val;
+#endif
#ifdef CONFIG_SERIAL
#ifdef CONFIG_SERIAL_TEXT_DEBUG
- ppc_md.progress = gen550_progress;
+ //ppc_md.progress = gen550_progress;
+ ppc_md.progress = sandpoint_progress;
#endif
ppc_md.early_serial_map = sandpoint_early_serial_map;
#endif
projects / linux-2.4.git / blobdiff