--- /dev/null
+/*\r
+ *\r
+ * ipg_macros.h\r
+ *\r
+ * Include file with macros for Gigabit Ethernet\r
+ * device driver for Network Interface Cards (NICs) utilizing the\r
+ * Tamarack Microelectronics Inc. IPG Gigabit or Triple Speed\r
+ * Ethernet Media Access Controller.\r
+ *\r
+ * Craig Rich\r
+ * Sundance Technology, Inc.\r
+ * 1485 Saratoga Avenue\r
+ * Suite 200\r
+ * San Jose, CA 95129\r
+ * 408 873 4117\r
+ * www.sundanceti.com\r
+ * craig_rich@sundanceti.com\r
+ *\r
+ * Rev Date Description\r
+ * --------------------------------------------------------------\r
+ * 0.1 3/30/01 New file created from original ipg.h\r
+ */\r
+\r
+/*\r
+ * Miscellaneous macros.\r
+ */\r
+\r
+/* Marco for printing debug statements.\r
+# define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " ## args) */\r
+#ifdef IPG_DEBUG\r
+# define IPG_DEBUG_MSG(args...) \r
+# define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " args)\r
+# define IPG_DUMPRFDLIST(args) ipg_dump_rfdlist(args)\r
+# define IPG_DUMPTFDLIST(args) ipg_dump_tfdlist(args)\r
+#else\r
+# define IPG_DEBUG_MSG(args...)\r
+# define IPG_DDEBUG_MSG(args...)\r
+# define IPG_DUMPRFDLIST(args)\r
+# define IPG_DUMPTFDLIST(args)\r
+#endif\r
+\r
+/*\r
+ * End miscellaneous macros.\r
+ */\r
+\r
+/*\r
+ * Register access macros.\r
+ */\r
+\r
+#ifdef USE_IO_OPS\r
+\r
+/* Use I/O access for IPG registers. */\r
+\r
+#define RD8 inb\r
+#define RD16 inw\r
+#define RD32 inl\r
+#define WR8 outb\r
+#define WR16 outw\r
+#define WR32 outl\r
+\r
+#else\r
+\r
+/* Use memory access for IPG registers. */\r
+\r
+#define RD8 readb\r
+#define RD16 readw\r
+#define RD32 readl\r
+#define WR8 writeb\r
+#define WR16 writew\r
+#define WR32 writel\r
+\r
+#endif\r
+\r
+#define IPG_READ_BYTEREG(regaddr) RD8(regaddr)\r
+\r
+#define IPG_READ_WORDREG(regaddr) RD16(regaddr)\r
+\r
+#define IPG_READ_LONGREG(regaddr) RD32(regaddr)\r
+\r
+#define IPG_WRITE_BYTEREG(regaddr, writevalue) WR8(writevalue, regaddr)\r
+\r
+#define IPG_WRITE_WORDREG(regaddr, writevalue) WR16(writevalue, regaddr)\r
+\r
+#define IPG_WRITE_LONGREG(regaddr, writevalue) WR32(writevalue, regaddr)\r
+\r
+#define IPG_READ_ASICCTRL(baseaddr) RD32(baseaddr + IPG_ASICCTRL)\r
+\r
+//Jesse20040128EEPROM_VALUE\r
+//#define IPG_WRITE_ASICCTRL(baseaddr, writevalue) WR32(IPG_AC_RSVD_MASK & (writevalue), baseaddr + IPG_ASICCTRL)\r
+#define IPG_WRITE_ASICCTRL(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ASICCTRL)\r
+\r
+#define IPG_READ_EEPROMCTRL(baseaddr) RD16(baseaddr + IPG_EEPROMCTRL)\r
+\r
+#define IPG_WRITE_EEPROMCTRL(baseaddr, writevalue) WR16(IPG_EC_RSVD_MASK & (writevalue), baseaddr + IPG_EEPROMCTRL)\r
+\r
+#define IPG_READ_EEPROMDATA(baseaddr) RD16(baseaddr + IPG_EEPROMDATA)\r
+\r
+#define IPG_WRITE_EEPROMDATA(baseaddr, writevalue) WR16(writevalue, (baseaddr + IPG_EEPROMDATA)\r
+\r
+#define IPG_READ_PHYSET(baseaddr) RD8(baseaddr + IPG_PHYSET)//Jesse20040128EEPROM_VALUE\r
+\r
+#define IPG_WRITE_PHYSET(baseaddr, writevalue) WR8(writevalue, baseaddr + IPG_PHYSET)//Jesse20040128EEPROM_VALUE\r
+\r
+#define IPG_READ_PHYCTRL(baseaddr) RD8(baseaddr + IPG_PHYCTRL)\r
+\r
+#define IPG_WRITE_PHYCTRL(baseaddr, writevalue) WR8(IPG_PC_RSVD_MASK & (writevalue), baseaddr + IPG_PHYCTRL)\r
+\r
+#define IPG_READ_RECEIVEMODE(baseaddr) RD8(baseaddr + IPG_RECEIVEMODE)\r
+\r
+#define IPG_WRITE_RECEIVEMODE(baseaddr, writevalue) WR8(IPG_RM_RSVD_MASK & (writevalue), baseaddr + IPG_RECEIVEMODE)\r
+\r
+#define IPG_READ_MAXFRAMESIZE(baseaddr) RD16(baseaddr + IPG_MAXFRAMESIZE)\r
+\r
+#define IPG_WRITE_MAXFRAMESIZE(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_MAXFRAMESIZE)\r
+\r
+#define IPG_READ_MACCTRL(baseaddr) RD32(baseaddr + IPG_MACCTRL)\r
+\r
+#define IPG_WRITE_MACCTRL(baseaddr, writevalue) WR32(IPG_MC_RSVD_MASK & (writevalue), baseaddr + IPG_MACCTRL)\r
+\r
+#define IPG_READ_INTSTATUSACK(baseaddr) RD16(baseaddr + IPG_INTSTATUSACK)\r
+\r
+#define IPG_READ_INTSTATUS(baseaddr) RD16(baseaddr + IPG_INTSTATUS)\r
+\r
+#define IPG_WRITE_INTSTATUS(baseaddr, writevalue) WR16(IPG_IS_RSVD_MASK & (writevalue), baseaddr + IPG_INTSTATUS)\r
+\r
+#define IPG_READ_INTENABLE(baseaddr) RD16(baseaddr + IPG_INTENABLE)\r
+\r
+#define IPG_WRITE_INTENABLE(baseaddr, writevalue) WR16(IPG_IE_RSVD_MASK & (writevalue), baseaddr + IPG_INTENABLE)\r
+\r
+#define IPG_READ_WAKEEVENT(baseaddr) RD8(baseaddr + IPG_WAKEEVENT)\r
+\r
+#define IPG_WRITE_WAKEEVENT(baseaddr, writevalue) WR8(writevalue, baseaddr + IPG_WAKEEVENT)\r
+\r
+#define IPG_READ_RXEARLYTHRESH(baseaddr) RD16(baseaddr + IPG_RXEARLYTHRESH)\r
+\r
+#define IPG_WRITE_RXEARLYTHRESH(baseaddr, writevalue) WR16(IPG_RE_RSVD_MASK & (writevalue), baseaddr + IPG_RXEARLYTHRESH)\r
+\r
+#define IPG_READ_TXSTARTTHRESH(baseaddr) RD32(baseaddr + IPG_TXSTARTTHRESH)\r
+\r
+#define IPG_WRITE_TXSTARTTHRESH(baseaddr, writevalue) WR32(IPG_TT_RSVD_MASK & (writevalue), baseaddr + IPG_TXSTARTTHRESH)\r
+\r
+#define IPG_READ_FIFOCTRL(baseaddr) RD16(baseaddr + IPG_FIFOCTRL)\r
+\r
+#define IPG_WRITE_FIFOCTRL(baseaddr, writevalue) WR16(IPG_FC_RSVD_MASK & (writevalue), baseaddr + IPG_FIFOCTRL)\r
+\r
+#define IPG_READ_RXDMAPOLLPERIOD(baseaddr) RD8(baseaddr + IPG_RXDMAPOLLPERIOD)\r
+\r
+#define IPG_WRITE_RXDMAPOLLPERIOD(baseaddr, writevalue) WR8(IPG_RP_RSVD_MASK & (writevalue), baseaddr + IPG_RXDMAPOLLPERIOD)\r
+\r
+#define IPG_READ_RXDMAURGENTTHRESH(baseaddr) RD8(baseaddr + IPG_RXDMAURGENTTHRESH)\r
+\r
+#define IPG_WRITE_RXDMAURGENTTHRESH(baseaddr, writevalue) WR8(IPG_RU_RSVD_MASK & (writevalue), baseaddr + IPG_RXDMAURGENTTHRESH)\r
+\r
+#define IPG_READ_RXDMABURSTTHRESH(baseaddr) RD8(baseaddr + IPG_RXDMABURSTTHRESH)\r
+\r
+#define IPG_WRITE_RXDMABURSTTHRESH(baseaddr, writevalue) WR8(writevalue, baseaddr + IPG_RXDMABURSTTHRESH)\r
+\r
+#define IPG_READ_RFDLISTPTR0(baseaddr) RD32(baseaddr + IPG_RFDLISTPTR0)\r
+\r
+#define IPG_WRITE_RFDLISTPTR0(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_RFDLISTPTR0)\r
+\r
+#define IPG_READ_RFDLISTPTR1(baseaddr) RD32(baseaddr + IPG_RFDLISTPTR1)\r
+\r
+#define IPG_WRITE_RFDLISTPTR1(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_RFDLISTPTR1)\r
+\r
+#define IPG_READ_TXDMAPOLLPERIOD(baseaddr) RD8(baseaddr + IPG_TXDMAPOLLPERIOD)\r
+\r
+#define IPG_WRITE_TXDMAPOLLPERIOD(baseaddr, writevalue) WR8(IPG_TP_RSVD_MASK & (writevalue), baseaddr + IPG_TXDMAPOLLPERIOD)\r
+\r
+#define IPG_READ_TXDMAURGENTTHRESH(baseaddr) RD8(baseaddr + IPG_TXDMAURGENTTHRESH)\r
+\r
+#define IPG_WRITE_TXDMAURGENTTHRESH(baseaddr, writevalue) WR8(IPG_TU_RSVD_MASK & (writevalue), baseaddr + IPG_TXDMAURGENTTHRESH)\r
+\r
+#define IPG_READ_TXDMABURSTTHRESH(baseaddr) RD8(baseaddr + IPG_TXDMABURSTTHRESH)\r
+\r
+#define IPG_WRITE_TXDMABURSTTHRESH(baseaddr, writevalue) WR8(IPG_TB_RSVD_MASK & (writevalue), baseaddr + IPG_TXDMABURSTTHRESH)\r
+\r
+#define IPG_READ_TFDLISTPTR0(baseaddr) RD32(baseaddr + IPG_TFDLISTPTR0)\r
+\r
+#define IPG_WRITE_TFDLISTPTR0(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_TFDLISTPTR0)\r
+\r
+#define IPG_READ_TFDLISTPTR1(baseaddr) RD32(baseaddr + IPG_TFDLISTPTR1)\r
+\r
+#define IPG_WRITE_TFDLISTPTR1(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_TFDLISTPTR1)\r
+\r
+#define IPG_READ_DMACTRL(baseaddr) RD32(baseaddr + IPG_DMACTRL)\r
+\r
+#define IPG_WRITE_DMACTRL(baseaddr, writevalue) WR32(IPG_DC_RSVD_MASK & (writevalue), baseaddr + IPG_DMACTRL)\r
+\r
+#define IPG_READ_TXSTATUS(baseaddr) RD32(baseaddr + IPG_TXSTATUS)\r
+\r
+#define IPG_WRITE_TXSTATUS(baseaddr, writevalue) WR32(IPG_TS_RSVD_MASK & (writevalue), baseaddr + IPG_TXSTATUS)\r
+\r
+#define IPG_READ_STATIONADDRESS0(baseaddr) RD16(baseaddr + IPG_STATIONADDRESS0)\r
+\r
+#define IPG_READ_STATIONADDRESS1(baseaddr) RD16(baseaddr + IPG_STATIONADDRESS1)\r
+\r
+#define IPG_READ_STATIONADDRESS2(baseaddr) RD16(baseaddr + IPG_STATIONADDRESS2)\r
+\r
+#define IPG_WRITE_STATIONADDRESS0(baseaddr,writevalue) WR16(writevalue,baseaddr + IPG_STATIONADDRESS0)//JES20040127EEPROM\r
+\r
+#define IPG_WRITE_STATIONADDRESS1(baseaddr,writevalue) WR16(writevalue,baseaddr + IPG_STATIONADDRESS1)//JES20040127EEPROM\r
+\r
+#define IPG_WRITE_STATIONADDRESS2(baseaddr,writevalue) WR16(writevalue,baseaddr + IPG_STATIONADDRESS2)//JES20040127EEPROM\r
+\r
+#define IPG_READ_COUNTDOWN(baseaddr) RD32(baseaddr + IPG_COUNTDOWN)\r
+\r
+#define IPG_WRITE_COUNTDOWN(baseaddr, writevalue) WR32(IPG_CD_RSVD_MASK & (writevalue), baseaddr + IPG_COUNTDOWN)\r
+\r
+#define IPG_READ_RXDMASTATUS(baseaddr) RD16(baseaddr + IPG_RXDMASTATUS)\r
+\r
+#define IPG_WRITE_HASHTABLE0(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_HASHTABLE0)\r
+\r
+#define IPG_WRITE_HASHTABLE1(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_HASHTABLE1)\r
+\r
+#define IPG_READ_STATISTICSMASK(baseaddr) RD32(baseaddr + IPG_STATISTICSMASK)\r
+\r
+#define IPG_WRITE_STATISTICSMASK(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_STATISTICSMASK)\r
+\r
+#define IPG_READ_RMONSTATISTICSMASK(baseaddr) RD32(baseaddr + IPG_RMONSTATISTICSMASK)\r
+\r
+#define IPG_WRITE_RMONSTATISTICSMASK(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_RMONSTATISTICSMASK)\r
+\r
+#define IPG_READ_VLANTAG(baseaddr) RD32(baseaddr + IPG_VLANTAG)\r
+\r
+#define IPG_WRITE_VLANTAG(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_VLANTAG)\r
+\r
+#define IPG_READ_FLOWONTHRESH(baseaddr) RD16(baseaddr + IPG_FLOWONTHRESH)\r
+\r
+#define IPG_WRITE_FLOWONTHRESH(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_FLOWONTHRESH)\r
+\r
+#define IPG_READ_FLOWOFFTHRESH(baseaddr) RD16(baseaddr + IPG_FLOWOFFTHRESH)\r
+\r
+#define IPG_WRITE_FLOWOFFTHRESH(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_FLOWOFFTHRESH)\r
+\r
+#define IPG_READ_DEBUGCTRL(baseaddr) RD16(baseaddr + IPG_DEBUGCTRL)\r
+\r
+#define IPG_WRITE_DEBUGCTRL(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_DEBUGCTRL)\r
+\r
+#define IPG_READ_RXDMAINTCTRL(baseaddr) RD32(baseaddr + IPG_RXDMAINTCTRL)\r
+\r
+#define IPG_WRITE_RXDMAINTCTRL(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_RXDMAINTCTRL)\r
+\r
+#define IPG_READ_TXJUMBOFRAMES(baseaddr) RD16(baseaddr + IPG_TXJUMBOFRAMES)\r
+\r
+#define IPG_WRITE_TXJUMBOFRAMES(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_TXJUMBOFRAMES)\r
+\r
+#define IPG_READ_UDPCHECKSUMERRORS(baseaddr) RD16(baseaddr + IPG_UDPCHECKSUMERRORS)\r
+\r
+#define IPG_WRITE_UDPCHECKSUMERRORS(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_UDPCHECKSUMERRORS)\r
+\r
+#define IPG_READ_IPCHECKSUMERRORS(baseaddr) RD16(baseaddr + IPG_IPCHECKSUMERRORS)\r
+\r
+#define IPG_WRITE_IPCHECKSUMERRORS(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_IPCHECKSUMERRORS)\r
+\r
+#define IPG_READ_TCPCHECKSUMERRORS(baseaddr) RD16(baseaddr + IPG_TCPCHECKSUMERRORS)\r
+\r
+#define IPG_WRITE_TCPCHECKSUMERRORS(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_TCPCHECKSUMERRORS)\r
+\r
+#define IPG_READ_RXJUMBOFRAMES(baseaddr) RD16(baseaddr + IPG_RXJUMBOFRAMES)\r
+\r
+#define IPG_WRITE_RXJUMBOFRAMES(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_RXJUMBOFRAMES)\r
+\r
+\r
+\r
+/* Statistic register read/write macros. */\r
+\r
+#define IPG_READ_OCTETRCVOK(baseaddr) RD32(baseaddr + IPG_OCTETRCVOK)\r
+\r
+#define IPG_WRITE_OCTETRCVOK(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_OCTETRCVOK)\r
+\r
+#define IPG_READ_MCSTOCTETRCVDOK(baseaddr) RD32(baseaddr + IPG_MCSTOCTETRCVDOK)\r
+\r
+#define IPG_WRITE_MCSTOCTETRCVDOK(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_MCSTOCTETRCVDOK)\r
+\r
+#define IPG_READ_BCSTOCTETRCVOK(baseaddr) RD32(baseaddr + IPG_BCSTOCTETRCVOK)\r
+\r
+#define IPG_WRITE_BCSTOCTETRCVOK(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_BCSTOCTETRCVOK)\r
+\r
+#define IPG_READ_FRAMESRCVDOK(baseaddr) RD32(baseaddr + IPG_FRAMESRCVDOK)\r
+\r
+#define IPG_WRITE_FRAMESRCVDOK(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_FRAMESRCVDOK)\r
+\r
+#define IPG_READ_MCSTFRAMESRCVDOK(baseaddr) RD32(baseaddr + IPG_MCSTFRAMESRCVDOK)\r
+\r
+#define IPG_WRITE_MCSTFRAMESRCVDOK(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_MCSTFRAMESRCVDOK)\r
+\r
+#define IPG_READ_BCSTFRAMESRCVDOK(baseaddr) RD16(baseaddr + IPG_BCSTFRAMESRCVDOK)\r
+\r
+#define IPG_WRITE_BCSTFRAMESRCVDOK(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_BCSTFRAMESRCVDOK)\r
+\r
+#define IPG_READ_MACCONTROLFRAMESRCVD(baseaddr) RD16(baseaddr + IPG_MACCONTROLFRAMESRCVD)\r
+\r
+#define IPG_WRITE_MACCONTROLFRAMESRCVD(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_MACCONTROLFRAMESRCVD)\r
+\r
+#define IPG_READ_FRAMETOOLONGERRRORS(baseaddr) RD16(baseaddr + IPG_FRAMETOOLONGERRRORS)\r
+\r
+#define IPG_WRITE_FRAMETOOLONGERRRORS(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_FRAMETOOLONGERRRORS)\r
+\r
+#define IPG_READ_INRANGELENGTHERRORS(baseaddr) RD16(baseaddr + IPG_INRANGELENGTHERRORS)\r
+\r
+#define IPG_WRITE_INRANGELENGTHERRORS(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_INRANGELENGTHERRORS)\r
+\r
+#define IPG_READ_FRAMECHECKSEQERRORS(baseaddr) RD16(baseaddr + IPG_FRAMECHECKSEQERRORS)\r
+\r
+#define IPG_WRITE_FRAMECHECKSEQERRORS(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_FRAMECHECKSEQERRORS)\r
+\r
+#define IPG_READ_FRAMESLOSTRXERRORS(baseaddr) RD16(baseaddr + IPG_FRAMESLOSTRXERRORS)\r
+\r
+#define IPG_WRITE_FRAMESLOSTRXERRORS(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_FRAMESLOSTRXERRORS)\r
+\r
+#define IPG_READ_FRAMESLOSTRXERRORS(baseaddr) RD16(baseaddr + IPG_FRAMESLOSTRXERRORS)\r
+\r
+#define IPG_WRITE_FRAMESLOSTRXERRORS(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_FRAMESLOSTRXERRORS)\r
+\r
+#define IPG_READ_OCTETXMTOK(baseaddr) RD32(baseaddr + IPG_OCTETXMTOK)\r
+\r
+#define IPG_WRITE_OCTETXMTOK(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_OCTETXMTOK)\r
+\r
+#define IPG_READ_MCSTOCTETXMTOK(baseaddr) RD32(baseaddr + IPG_MCSTOCTETXMTOK)\r
+\r
+#define IPG_WRITE_MCSTOCTETXMTOK(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_MCSTOCTETXMTOK)\r
+\r
+#define IPG_READ_BCSTOCTETXMTOK(baseaddr) RD32(baseaddr + IPG_BCSTOCTETXMTOK)\r
+\r
+#define IPG_WRITE_BCSTOCTETXMTOK(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_BCSTOCTETXMTOK)\r
+\r
+#define IPG_READ_FRAMESXMTDOK(baseaddr) RD32(baseaddr + IPG_FRAMESXMTDOK)\r
+\r
+#define IPG_WRITE_FRAMESXMTDOK(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_FRAMESXMTDOK)\r
+\r
+#define IPG_READ_MCSTFRAMESXMTDOK(baseaddr) RD32(baseaddr + IPG_MCSTFRAMESXMTDOK)\r
+\r
+#define IPG_WRITE_MCSTFRAMESXMTDOK(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_MCSTFRAMESXMTDOK)\r
+\r
+#define IPG_READ_FRAMESWDEFERREDXMT(baseaddr) RD32(baseaddr + IPG_FRAMESWDEFERREDXMT)\r
+\r
+#define IPG_WRITE_FRAMESWDEFERREDXMT(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_FRAMESWDEFERREDXMT)\r
+\r
+#define IPG_READ_LATECOLLISIONS(baseaddr) RD32(baseaddr + IPG_LATECOLLISIONS)\r
+\r
+#define IPG_WRITE_LATECOLLISIONS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_LATECOLLISIONS)\r
+\r
+#define IPG_READ_MULTICOLFRAMES(baseaddr) RD32(baseaddr + IPG_MULTICOLFRAMES)\r
+\r
+#define IPG_WRITE_MULTICOLFRAMES(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_MULTICOLFRAMES)\r
+\r
+#define IPG_READ_SINGLECOLFRAMES(baseaddr) RD32(baseaddr + IPG_SINGLECOLFRAMES)\r
+\r
+#define IPG_WRITE_SINGLECOLFRAMES(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_SINGLECOLFRAMES)\r
+\r
+#define IPG_READ_BCSTFRAMESXMTDOK(baseaddr) RD16(baseaddr + IPG_BCSTFRAMESXMTDOK)\r
+\r
+#define IPG_WRITE_BCSTFRAMESXMTDOK(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_BCSTFRAMESXMTDOK)\r
+\r
+#define IPG_READ_CARRIERSENSEERRORS(baseaddr) RD16(baseaddr + IPG_CARRIERSENSEERRORS)\r
+\r
+#define IPG_WRITE_CARRIERSENSEERRORS(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_CARRIERSENSEERRORS)\r
+\r
+#define IPG_READ_MACCONTROLFRAMESXMTDOK(baseaddr) RD16(baseaddr + IPG_MACCONTROLFRAMESXMTDOK)\r
+\r
+#define IPG_WRITE_MACCONTROLFRAMESXMTDOK(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_MACCONTROLFRAMESXMTDOK)\r
+\r
+#define IPG_READ_FRAMESABORTXSCOLLS(baseaddr) RD16(baseaddr + IPG_FRAMESABORTXSCOLLS)\r
+\r
+#define IPG_WRITE_FRAMESABORTXSCOLLS(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_FRAMESABORTXSCOLLS)\r
+\r
+#define IPG_READ_FRAMESWEXDEFERRAL(baseaddr) RD16(baseaddr + IPG_FRAMESWEXDEFERRAL)\r
+\r
+#define IPG_WRITE_FRAMESWEXDEFERRAL(baseaddr, writevalue) WR16(writevalue, baseaddr + IPG_FRAMESWEXDEFERRAL)\r
+\r
+/* RMON statistic register read/write macros. */\r
+\r
+#define IPG_READ_ETHERSTATSCOLLISIONS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSCOLLISIONS)\r
+\r
+#define IPG_WRITE_ETHERSTATSCOLLISIONS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSCOLLISIONS)\r
+\r
+#define IPG_READ_ETHERSTATSOCTETSTRANSMIT(baseaddr) RD32(baseaddr + IPG_ETHERSTATSOCTETSTRANSMIT)\r
+\r
+#define IPG_WRITE_ETHERSTATSOCTETSTRANSMIT(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSOCTETSTRANSMIT)\r
+\r
+#define IPG_READ_ETHERSTATSPKTSTRANSMIT(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTSTRANSMIT)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTSTRANSMIT(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTSTRANSMIT)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS64OCTESTSTRANSMIT(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS64OCTESTSTRANSMIT)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS64OCTESTSTRANSMIT(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS64OCTESTSTRANSMIT)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT)\r
+\r
+#define IPG_READ_ETHERSTATSCRCALIGNERRORS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSCRCALIGNERRORS)\r
+\r
+#define IPG_WRITE_ETHERSTATSCRCALIGNERRORS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSCRCALIGNERRORS)\r
+\r
+#define IPG_READ_ETHERSTATSUNDERSIZEPKTS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSUNDERSIZEPKTS)\r
+\r
+#define IPG_WRITE_ETHERSTATSUNDERSIZEPKTS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSUNDERSIZEPKTS)\r
+\r
+#define IPG_READ_ETHERSTATSFRAGMENTS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSFRAGMENTS)\r
+\r
+#define IPG_WRITE_ETHERSTATSFRAGMENTS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSFRAGMENTS)\r
+\r
+#define IPG_READ_ETHERSTATSJABBERS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSJABBERS)\r
+\r
+#define IPG_WRITE_ETHERSTATSJABBERS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSJABBERS)\r
+\r
+#define IPG_READ_ETHERSTATSOCTETS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSOCTETS)\r
+\r
+#define IPG_WRITE_ETHERSTATSOCTETS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSOCTETS)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS64OCTESTS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS64OCTESTS)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS64OCTESTS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS64OCTESTS)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS65TO127OCTESTS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS65TO127OCTESTS)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS65TO127OCTESTS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS65TO127OCTESTS)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS128TO255OCTESTS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS128TO255OCTESTS)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS128TO255OCTESTS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS128TO255OCTESTS)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS256TO511OCTESTS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS256TO511OCTESTS)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS256TO511OCTESTS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS256TO511OCTESTS)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS512TO1023OCTESTS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS512TO1023OCTESTS)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS512TO1023OCTESTS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS512TO1023OCTESTS)\r
+\r
+#define IPG_READ_ETHERSTATSPKTS1024TO1518OCTESTS(baseaddr) RD32(baseaddr + IPG_ETHERSTATSPKTS1024TO1518OCTESTS)\r
+\r
+#define IPG_WRITE_ETHERSTATSPKTS1024TO1518OCTESTS(baseaddr, writevalue) WR32(writevalue, baseaddr + IPG_ETHERSTATSPKTS1024TO1518OCTESTS)\r
+\r
+/*\r
+ * End register access macros.\r
+ */\r
+\r
+/* end ipg_macros.h */\r
projects / linux-2.4.git / blobdiff