3 * Copyright (C) Igor Sysoev
8 * The ppc assembler treats ";" as comment, so we have to use "\n".
9 * The minus in "bne-" is a hint for the branch prediction unit that
10 * this branch is unlikely to be taken.
11 * The "1b" means the nearest backward label "1" and the "1f" means
12 * the nearest forward label "1".
14 * The "b" means that the base registers can be used only, i.e.
15 * any register except r0. The r0 register always has a zero value and
16 * could not be used in "addi r0, r0, 1".
17 * The "=&b" means that no input registers can be used.
19 * "sync" read and write barriers
20 * "isync" read barrier, is faster than "sync"
21 * "eieio" write barrier, is faster than "sync"
22 * "lwsync" write barrier, is faster than "eieio" on ppc64
25 #if (NGX_PTR_SIZE == 8)
27 static ngx_inline ngx_atomic_uint_t
28 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
29 ngx_atomic_uint_t set)
31 ngx_atomic_uint_t res, temp;
35 " li %0, 0 \n" /* preset "0" to "res" */
36 " lwsync \n" /* write barrier */
38 " ldarx %1, 0, %2 \n" /* load from [lock] into "temp" */
39 /* and store reservation */
40 " cmpd %1, %3 \n" /* compare "temp" and "old" */
41 " bne- 2f \n" /* not equal */
42 " stdcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */
44 " bne- 1b \n" /* the reservation was cleared */
45 " isync \n" /* read barrier */
46 " li %0, 1 \n" /* set "1" to "res" */
49 : "=&b" (res), "=&b" (temp)
50 : "b" (lock), "b" (old), "b" (set)
57 static ngx_inline ngx_atomic_int_t
58 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
60 ngx_atomic_uint_t res, temp;
64 " lwsync \n" /* write barrier */
65 "1: ldarx %0, 0, %2 \n" /* load from [value] into "res" */
66 /* and store reservation */
67 " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */
68 " stdcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */
70 " bne- 1b \n" /* try again if reservation was cleared */
71 " isync \n" /* read barrier */
73 : "=&b" (res), "=&b" (temp)
74 : "b" (value), "b" (add)
82 #define ngx_memory_barrier() \
83 __asm__ volatile ("isync \n lwsync \n" ::: "memory")
85 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory")
90 static ngx_inline ngx_atomic_uint_t
91 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
92 ngx_atomic_uint_t set)
94 ngx_atomic_uint_t res, temp;
98 " li %0, 0 \n" /* preset "0" to "res" */
99 " eieio \n" /* write barrier */
101 " lwarx %1, 0, %2 \n" /* load from [lock] into "temp" */
102 /* and store reservation */
103 " cmpw %1, %3 \n" /* compare "temp" and "old" */
104 " bne- 2f \n" /* not equal */
105 " stwcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */
107 " bne- 1b \n" /* the reservation was cleared */
108 " isync \n" /* read barrier */
109 " li %0, 1 \n" /* set "1" to "res" */
112 : "=&b" (res), "=&b" (temp)
113 : "b" (lock), "b" (old), "b" (set)
120 static ngx_inline ngx_atomic_int_t
121 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
123 ngx_atomic_uint_t res, temp;
127 " eieio \n" /* write barrier */
128 "1: lwarx %0, 0, %2 \n" /* load from [value] into "res" */
129 /* and store reservation */
130 " add %1, %0, %3 \n" /* "res" + "add" store in "temp" */
131 " stwcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */
133 " bne- 1b \n" /* try again if reservation was cleared */
134 " isync \n" /* read barrier */
136 : "=&b" (res), "=&b" (temp)
137 : "b" (value), "b" (add)
145 #define ngx_memory_barrier() \
146 __asm__ volatile ("isync \n eieio \n" ::: "memory")
148 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory")
154 #define ngx_cpu_pause()