3 * Copyright (C) Igor Sysoev
8 #define NGX_SMP_LOCK "lock;"
26 * The "r" means the general register.
27 * The "=a" and "a" are the %eax register.
28 * Although we can return result in any register, we use "a" because it is
29 * used in cmpxchgl anyway. The result is actually in %al but not in %eax,
30 * however, as the code is inlined gcc can test %al as well as %eax,
31 * and icc adds "movzbl %al, %eax" by itself.
33 * The "cc" means that flags were changed.
36 static ngx_inline ngx_atomic_uint_t
37 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
38 ngx_atomic_uint_t set)
48 : "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory");
62 * The "+r" means the general register.
63 * The "cc" means that flags were changed.
67 #if !(( __GNUC__ == 2 && __GNUC_MINOR__ <= 7 ) || ( __INTEL_COMPILER >= 800 ))
70 * icc 8.1 and 9.0 compile broken code with -march=pentium4 option:
71 * ngx_atomic_fetch_add() always return the input "add" value,
72 * so we use the gcc 2.7 version.
74 * icc 8.1 and 9.0 with -march=pentiumpro option or icc 7.1 compile
78 static ngx_inline ngx_atomic_int_t
79 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
86 : "+r" (add) : "m" (*value) : "cc", "memory");
95 * gcc 2.7 does not support "+r", so we have to use the fixed
96 * %eax ("=a" and "a") and this adds two superfluous instructions in the end
97 * of code, something like this: "mov %eax, %edx / mov %edx, %eax".
100 static ngx_inline ngx_atomic_int_t
101 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
103 ngx_atomic_uint_t old;
110 : "=a" (old) : "m" (*value), "a" (add) : "cc", "memory");
119 * on x86 the write operations go in a program order, so we need only
120 * to disable the gcc reorder optimizations
123 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory")
125 /* old as does not support "pause" opcode */
126 #define ngx_cpu_pause() __asm__ (".byte 0xf3, 0x90")