rpi jtag to ulx3s ecp5 85

diff --git a/ulx3s-85/fpga.cfg b/ulx3s-85/fpga.cfg
new file mode 100644 (file)
index 0000000..bf20007
--- /dev/null
+++ b/ulx3s-85/fpga.cfg
@@ -0,0 +1,10 @@
+# This is the ID for the *FPGA's* chip TAP. (note this ID is for 85F version
+# of ULX3S -- if you have a different ECP5 size you can either enter the
+# correct ID for your ECP5, or remove the -expected-id part). We are going to
+# expose processor debug through a pair of custom DRs on this TAP.
+
+set _CHIPNAME lfe5u85
+# 85f
+jtag newtap lfe5u85 hazard3 -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5
+# 25f
+#jtag newtap lfe5u85 hazard3 -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5

diff --git a/ulx3s-85/openocd.sh b/ulx3s-85/openocd.sh
new file mode 100755 (executable)
index 0000000..f204e7f
--- /dev/null
+++ b/ulx3s-85/openocd.sh
@@ -0,0 +1,12 @@
+#!/bin/sh -xe
+
+#openocd -f ../rpi4-jtag.cfg -f fpga.cfg
+#openocd -f ../rpi4-jtag.cfg -f saxon.cfg
+
+# cp /fpga/SaxonSoc/cpu0.yaml .
+
+SAXON_ROOT=/home/pi
+# rsync -rav /fpga/openocd_riscv/openocd_riscv $SAXON_ROOT
+SAXON_BSP_PATH=/home/pi/openocd-rpi2-stm32/ulx3s-85/
+# rsync -rav /fpga/SaxonSoc/bsp/radiona/ulx3s/smp/openocd/ openocd/
+$SAXON_ROOT/openocd_riscv/src/openocd -s $SAXON_ROOT/openocd_riscv/tcl -s $SAXON_BSP_PATH/openocd -c 'set CPU0_YAML cpu0.yaml' -f ../rpi4-jtag.cfg -f saxon.cfg -f soc_init.cfg

diff --git a/ulx3s-85/saxon.cfg b/ulx3s-85/saxon.cfg
new file mode 100644 (file)
index 0000000..327522a
--- /dev/null
+++ b/ulx3s-85/saxon.cfg
@@ -0,0 +1,9 @@
+# This is the ID for the *FPGA's* chip TAP. (note this ID is for 85F version
+# of ULX3S -- if you have a different ECP5 size you can either enter the
+# correct ID for your ECP5, or remove the -expected-id part).
+
+set _CHIPNAME fpga_spinal
+# 85f
+jtag newtap $_CHIPNAME bridge -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5
+# 25f
+#jtag newtap lfe5u85 hazard3 -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5