git.rot13.org Git - simavr/commit - simavr/sim/sim

author	Michel Pollet <buserror@gmail.com>
	Mon, 30 Nov 2009 21:36:55 +0000 (21:36 +0000)
committer	Michel Pollet <buserror@gmail.com>
	Mon, 30 Nov 2009 21:36:55 +0000 (21:36 +0000)
commit	6dc37c42aa8c60ee6e41f20718c858e1374dd2c6
tree	3d51addeb1fe009eac6d778586e079b90b1cb1f0	tree \| snapshot
parent	d8e5774323d5408e119b5fa3cce1c73c7345e8f7	commit \| diff

Cores, decoder, uart, ioports - lots of changes

+ Cores now use eeprom declare macro
+ Cores now use the "TXCE" etc bits
+ Uart now raise TXC interupt/flag
+ ioports now use new internal IRQ system
+ New command line options for mcu, freq and trace
+ Decoder updates:
  - Fixed the last known "crash" bug.
  - Added cycles to most multi-cycle opcodes.
  - Added optional stack frame watcher
  - Skip instruction now handle 32 bits skips

Signed-off-by: Michel Pollet <buserror@gmail.com>

15 files changed:

Unnamed repository; edit this file 'description' to name the repository.

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simavr/Makefile		diff \| blob \| history
simavr/cores/sim_mega644.c		diff \| blob \| history
simavr/cores/sim_megax8.h		diff \| blob \| history
simavr/cores/sim_tiny85.c		diff \| blob \| history
simavr/sim/avr_eeprom.c		diff \| blob \| history
simavr/sim/avr_eeprom.h		diff \| blob \| history
simavr/sim/avr_ioport.c		diff \| blob \| history
simavr/sim/avr_ioport.h		diff \| blob \| history
simavr/sim/avr_uart.c		diff \| blob \| history
simavr/sim/avr_uart.h		diff \| blob \| history
simavr/sim/sim_core.c		diff \| blob \| history
simavr/sim/sim_core.h		diff \| blob \| history
simavr/sim/sim_elf.c		diff \| blob \| history
simavr/sim/simavr.c		diff \| blob \| history
simavr/sim/simavr.h		diff \| blob \| history