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(parent: eab7a03) | patch
UART: Delay TX interupt a few cycles
authorMichel Pollet <buserror@gmail.com>
Tue, 15 Dec 2009 21:37:53 +0000 (21:37 +0000)
committerMichel Pollet <buserror@gmail.com>
Tue, 15 Dec 2009 21:37:53 +0000 (21:37 +0000)
commit50176cc716e54b91ab9226c0f33b5234d2b58f40
treef6eaed680e766d3ba4e4c30f3f4a69fe5487f80ctree | snapshot
parenteab7a03e7ab811e50497f1316f6dac1b622d007fcommit | diff
UART: Delay TX interupt a few cycles

Also clear the "buffer empty" flag when UDR is written

Signed-off-by: Michel Pollet <buserror@gmail.com>
simavr/sim/avr_uart.c diff | blob | history
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