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(parent: 3fa1bd3) | patch
mega1280: Add missing timers 4 and 5
authorJakob Gruber <jakob.gruber@gmail.com>
Sat, 4 Aug 2012 13:10:05 +0000 (15:10 +0200)
committerJakob Gruber <jakob.gruber@gmail.com>
Sun, 5 Aug 2012 11:00:53 +0000 (13:00 +0200)
commitcadc3dad50aa26c32d76359ce707220919d4cf2d
tree5650bff67022779e267b8015f71d1f834cd09dc6tree | snapshot
parent3fa1bd3e503bf7653f9df06e30b2c1e815ccc91acommit | diff
mega1280: Add missing timers 4 and 5

These are 16-bit timers similar to Timer1 and Timer3.
simavr/cores/sim_mega1280.c [changed mode: 0755->0644] diff | blob | history
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