1 `include "i2c_bridge.v"
16 output exp_pin_3, exp_pin_4,
17 output exp_pin_5, exp_pin_6,
18 output exp_pin_7, exp_pin_8,
20 input spi_sclk, spi_mosi, spi_cs0,
34 .out0_hz(16000000),.out0_tol_hz(0) ,
35 .out1_hz(96000000), .out1_deg( 0), .out1_tol_hz(0)//,
36 //.out2_hz(60000000), .out2_deg(180), .out2_tol_hz(0),
44 assign mhz_16 = clocks[0];
45 assign mhz_96 = clocks[1];
48 assign exp_pin_4 = clocks[0];
49 assign exp_pin_8 = clocks[1];
51 assign exp_pin_4 = rtc_scl;
52 assign exp_pin_8 = rtc_sda;
55 assign green_led_d7 = rtc_scl;
56 assign orange_led_d8 = rtc_sda;
57 assign red_led_d5 = tuner_scl;
58 assign yellow_led_d6 = tuner_sda;
60 assign green_led_d7 = 0;
61 assign orange_led_d8 = 0;
62 //assign red_led_d5 = tuner_scl;
63 assign yellow_led_d6 = 0;
65 localparam bridge_clk_div = 3; // div = 1+2^n, 24/(1+2^2)=4 MHz
66 reg [bridge_clk_div:0] bridge_cnt;
67 always @(posedge clk) // 24 MHz
69 if(bridge_cnt[bridge_clk_div])
72 bridge_cnt <= bridge_cnt + 1;
74 wire clk_bridge_en = bridge_cnt[bridge_clk_div];
76 wire [1:0] i2c_sda_i = {rtc_sda, tuner_sda};
78 i2c_bridge i2c_sda_bridge_i
81 .clk_en(clk_bridge_en),
85 assign rtc_sda = i2c_sda_t[1] ? 1'bz : 1'b0;
86 assign tuner_sda = i2c_sda_t[0] ? 1'bz : 1'b0;
88 wire [1:0] i2c_scl_i = {rtc_scl, tuner_scl};
90 i2c_bridge i2c_scl_bridge_i
93 .clk_en(clk_bridge_en),
97 assign rtc_scl = i2c_scl_t[1] ? 1'bz : 1'b0;
98 assign tuner_scl = i2c_scl_t[0] ? 1'bz : 1'b0;