git.rot13.org Git - trilby-hat-fpga/blob - i2c.v

   1 `default_nettype none
   2
   3 `include "i2c_bridge.v"
   4 `include "ecp5pll.sv"
   5 `include "SPI_slave.v"
   6
   7 module top(
   8         input clk,
   9
  10         inout rtc_sda,
  11         inout rtc_scl,
  12
  13         inout tuner_sda,
  14         inout tuner_scl,
  15
  16         output mhz_16,mhz_96,
  17
  18         output exp_pin_3, exp_pin_4,
  19         output exp_pin_5, exp_pin_6,
  20         output exp_pin_7, exp_pin_8,
  21
  22         input spi_sclk, spi_mosi, spi_cs0,
  23         output spi_miso,
  24
  25         input a2dq2, a2dq3, a2dq4, a2dq5, a2dq6, a2dq7, a2dq8, a2dq9, a2dq10, a2dq11, a2dq12, a2dq13,
  26
  27         output green_led_d7,
  28         output orange_led_d8,
  29         output red_led_d5,
  30         output yellow_led_d6
  31
  32 );
  33
  34         wire [3:0] clocks;
  35         ecp5pll
  36         #(
  37                 .in_hz(24000000),
  38                 .out0_hz(16000000),.out0_tol_hz(0) ,
  39                 .out1_hz(96000000), .out1_deg( 0), .out1_tol_hz(0),
  40                 .out2_hz(192000000), .out2_deg(0), .out2_tol_hz(0)
  41         )
  42         ecp5pll_inst
  43         (
  44                 .clk_i(clk),
  45                 .clk_o(clocks)
  46         );
  47
  48         assign mhz_16 = clocks[0];
  49         assign mhz_96 = clocks[1];
  50
  51 /*
  52         assign exp_pin_4 = clocks[0];
  53         assign exp_pin_8 = clocks[1];
  54 */
  55         assign exp_pin_4 = rtc_scl;
  56         assign exp_pin_8 = rtc_sda;
  57
  58 /*
  59         assign green_led_d7  = rtc_scl;
  60         assign orange_led_d8 = rtc_sda;
  61         assign red_led_d5    = tuner_scl;
  62         assign yellow_led_d6 = tuner_sda;
  63 */
  64         assign green_led_d7  = 0;
  65         assign orange_led_d8 = 0;
  66         //assign red_led_d5    = tuner_scl;
  67         assign yellow_led_d6 = 0;
  68
  69   localparam bridge_clk_div = 3; // div = 1+2^n, 24/(1+2^2)=4 MHz
  70   reg [bridge_clk_div:0] bridge_cnt;
  71   always @(posedge clk) // 24 MHz
  72   begin
  73     if(bridge_cnt[bridge_clk_div])
  74       bridge_cnt <= 0;
  75     else
  76       bridge_cnt <= bridge_cnt + 1;
  77   end
  78   wire clk_bridge_en = bridge_cnt[bridge_clk_div];
  79
  80   wire [1:0] i2c_sda_i = {rtc_sda, tuner_sda};
  81   wire [1:0] i2c_sda_t;
  82   i2c_bridge i2c_sda_bridge_i
  83   (
  84     .clk(mhz_96),
  85     .clk_en(clk_bridge_en),
  86     .i(i2c_sda_i),
  87     .t(i2c_sda_t)
  88   );
  89   assign rtc_sda = i2c_sda_t[1] ? 1'bz : 1'b0;
  90   assign tuner_sda = i2c_sda_t[0] ? 1'bz : 1'b0;
  91
  92   wire [1:0] i2c_scl_i = {rtc_scl, tuner_scl};
  93   wire [1:0] i2c_scl_t;
  94   i2c_bridge i2c_scl_bridge_i
  95   (
  96     .clk(clk),
  97     .clk_en(clk_bridge_en),
  98     .i(i2c_scl_i),
  99     .t(i2c_scl_t)
 100   );
 101   assign rtc_scl = i2c_scl_t[1] ? 1'bz : 1'b0;
 102   assign tuner_scl = i2c_scl_t[0] ? 1'bz : 1'b0;
 103
 104         SPI_slave SPI_slave(
 105                 .clk(clocks[2]),
 106                 .SCK(spi_sclk),
 107                 .MOSI(spi_mosi),
 108                 .MISO(spi_miso),
 109                 .SSEL(spi_cs0),
 110                 .LED(red_led_d5),
 111                 .d0(a2dq2),
 112                 .d1(a2dq3),
 113                 .d2(a2dq4),
 114                 .d3(a2dq5),
 115                 .d4(a2dq6),
 116                 .d5(a2dq7),
 117                 .d6(a2dq8),
 118                 .d7(a2dq9),
 119                 .d8(a2dq10),
 120                 .d9(a2dq11),
 121                 .d10(a2dq12),
 122                 .d11(a2dq13),
 123         );
 124
 125 endmodule