5 input wire clk_en, // 1-clk pulse, repeats 1.5-6 MHz
6 input wire [1:0] i, // inputs
7 output wire [1:0] t // tristate 0->0 1->Z
9 reg [1:0] state, next_state;
28 if(i[0]==0 && i[1]==1)
30 else if(i[1]==0 && i[0]==1)
41 assign t[1] = state == 2'd0 ? 0:1;
42 assign t[0] = state == 2'd1 ? 0:1;