all: ${PROJ}.bit
%.json: %.v
- yosys -p "synth_ecp5 -json $@" $<
+ yosys -p "read_verilog ${PROJ}.v ; synth_ecp5 ; write_json $@" -E .$(basename $@).d $<
%_out.config: %.json
nextpnr-ecp5 --json $< --textcfg $@ --45k --package CABGA381 --lpf trilby.lpf
rm -f *.svf *.bit *.config *.json
.PHONY: prog clean
+-include .*.d