X-Git-Url: http://git.rot13.org/?p=trilby-hat-fpga;a=blobdiff_plain;f=trilby.lpf;h=6c14b21381fc0db0257e623b7be618889ef942e6;hp=85d0cecfdfd4eb09a222c6a36d89e87ae9c21dc4;hb=f4e9affa08efc13dc8cf2fe3a67a8ca7400903e0;hpb=7120a1d20fb209a5a380629c773703383575f041

diff --git a/trilby.lpf b/trilby.lpf
index 85d0cec..6c14b21 100644
--- a/trilby.lpf
+++ b/trilby.lpf
@@ -13,18 +13,33 @@ LOCATE  COMP  "clk"  SITE  "U16"; # CLK 24Mhz TCXO
 IOBUF PORT "clk" PULLMODE=NONE IO_TYPE=LVCMOS33; # ? 33?
 FREQUENCY PORT "clk" 24 MHZ;
 
-LOCATE  COMP  "a2dq10"  SITE  "C17"; # in
-LOCATE  COMP  "a2dq11"  SITE  "A18";
-LOCATE  COMP  "a2dq12"  SITE  "A19";
-LOCATE  COMP  "a2dq13"  SITE  "B19";
-LOCATE  COMP  "a2dq2"  SITE  "B12";
-LOCATE  COMP  "a2dq3"  SITE  "D15";
-LOCATE  COMP  "a2dq4"  SITE  "C15";
-LOCATE  COMP  "a2dq5"  SITE  "B15";
-LOCATE  COMP  "a2dq6"  SITE  "E15";
-LOCATE  COMP  "a2dq7"  SITE  "C16";
-LOCATE  COMP  "a2dq8"  SITE  "D16";
-LOCATE  COMP  "a2dq9"  SITE  "B17";
+
+# LTC2226CUH - in
+# 12bit, 25Msps, 3V ADC
+# clk - 24mhz tcxo
+#
+# schematics implies that ADC has 14 bits, it has only 12
+# my guess it that previous version had 14 bit ADC, so
+# a2dq0 and a2dq1 are not used in original vhdl
+
+LOCATE  COMP  "a2dq0"   SITE  "D12"; # -- not used in hdl (12-bit ADC), from schematic
+LOCATE  COMP  "a2dq1"   SITE  "C12"; # -- not used
+LOCATE  COMP  "a2dq2"   SITE  "B12"; # D0
+LOCATE  COMP  "a2dq3"   SITE  "D15"; # D1
+LOCATE  COMP  "a2dq4"   SITE  "C15"; # D2
+LOCATE  COMP  "a2dq5"   SITE  "B15"; # D3
+LOCATE  COMP  "a2dq6"   SITE  "E15"; # D4
+LOCATE  COMP  "a2dq7"   SITE  "C16"; # D5
+LOCATE  COMP  "a2dq8"   SITE  "D16"; # D6
+LOCATE  COMP  "a2dq9"   SITE  "B17"; # D7
+LOCATE  COMP  "a2dq10"  SITE  "C17"; # D8
+LOCATE  COMP  "a2dq11"  SITE  "A18"; # D9
+LOCATE  COMP  "a2dq12"  SITE  "A19"; # D10
+LOCATE  COMP  "a2dq13"  SITE  "B19"; # D11 MSB
+
+LOCATE  COMP  "a2d_of"  SITE  "B20"; # over/under flow
+
+
 
 LOCATE  COMP  "audio_l"  SITE  "H20"; # out
 LOCATE  COMP  "audio_r"  SITE  "K18"; # out
@@ -68,7 +83,7 @@ IOBUF PORT "yellow_led_d6" IO_TYPE=LVCMOS33;
 
 
 LOCATE  COMP  "mhz_16"  SITE  "L20"; # out
-LOCATE  COMP  "mhz_96"  SITE  "L17"; # out
+LOCATE  COMP  "mhz_96"  SITE  "L17"; # out - ADE-1 frequency mixer LO
 
 
 # reaspberry pi header
@@ -137,7 +152,7 @@ IOBUF PORT "rpi_pin_38"  IO_TYPE=LVCMOS33;
 IOBUF PORT "rpi_pin_40"  IO_TYPE=LVCMOS33;
 
 
-LOCATE  COMP  "tuner_hf"  SITE  "D8";
+LOCATE  COMP  "tuner_hf"   SITE  "D8"; # ADG918 switch lf/hf
 LOCATE  COMP  "tuner_scl"  SITE  "C6";
 LOCATE  COMP  "tuner_sda"  SITE  "C7";
 
@@ -148,7 +163,7 @@ IOBUF PORT "tuner_sda"  IO_TYPE=LVCMOS33;
 LOCATE  COMP  "unused"  SITE  "B11";
 
 #PLL
-LOCATE  COMP  "I518/pll_24_to_96_inst/PLLInst_0"  SITE  "PLL_BR0" ;
+#LOCATE  COMP  "I518/pll_24_to_96_inst/PLLInst_0"  SITE  "PLL_BR0" ;
 
 #FREQUENCY NET "N_355" 16.000000 MHz ;
 #FREQUENCY NET "clkfast" 96.000000 MHz ;