we need read_verilog instead of read
authorDobrica Pavlinusic <dpavlin@rot13.org>
Fri, 21 Jan 2022 11:44:55 +0000 (12:44 +0100)
committerDobrica Pavlinusic <dpavlin@rot13.org>
Fri, 21 Jan 2022 11:44:55 +0000 (12:44 +0100)
commit302c67c98a30def10b8b8845c6f820d9e8da130b
tree5f968cd6f2aab35a6b3e913ffab7b79cf0e90189
parent8b270f00c4156c8960f0326db2bc74b45fa84287
we need read_verilog instead of read

Otherwise, all modules in recent yosys become abstract, and
optimized out
Makefile