we need read_verilog instead of read

Otherwise, all modules in recent yosys become abstract, and
optimized out

diff --git a/Makefile b/Makefile
index 34477b7..ed75e6e 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@ TRELLIS?=/usr/share/trellis
 all: ${PROJ}.bit
 
 %.json: %.v
-       yosys -p "synth_ecp5 -json $@" $<
+       yosys -p "read_verilog ${PROJ}.v ; synth_ecp5 ; write_json $@" -E .$(basename $@).d $<
 
 %_out.config: %.json
        nextpnr-ecp5 --json $< --textcfg $@ --45k --package CABGA381 --lpf trilby.lpf
@@ -22,3 +22,4 @@ clean:
        rm -f *.svf *.bit *.config *.json
 
 .PHONY: prog clean
+-include .*.d