fix clk pin

diff --git a/trilby.lpf b/trilby.lpf
index 535e9f8..b3143a3 100644 (file)
--- a/trilby.lpf
+++ b/trilby.lpf
@@ -7,12 +7,13 @@
 \r
 #SYSCONFIG SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF DONE_EX=OFF DONE_OD=ON DONE_PULL=ON MCCLK_FREQ=2.4 TRANSFR=OFF CONFIG_IOVOLTAGE=2.5 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF CONFIG_MODE=JTAG ;\r
 \r
-LOCATE  COMP  "AGC_A"  SITE  "E8";\r
+LOCATE  COMP  "AGC_A"  SITE  "E8"; # out\r
 \r
 LOCATE  COMP  "clk"  SITE  "U16"; # CLK 24Mhz TCXO\r
-IOBUF PORT "clk" IO_TYPE=LVCMOS25; # ? 33?\r
+IOBUF PORT "clk" PULLMODE=NONE IO_TYPE=LVCMOS25; # ? 33?\r
+FREQUENCY PORT "clk" 24 MHZ;\r
 \r
-LOCATE  COMP  "a2dq10"  SITE  "C17";\r
+LOCATE  COMP  "a2dq10"  SITE  "C17"; # in\r
 LOCATE  COMP  "a2dq11"  SITE  "A18";\r
 LOCATE  COMP  "a2dq12"  SITE  "A19";\r
 LOCATE  COMP  "a2dq13"  SITE  "B19";\r
@@ -25,8 +26,8 @@ LOCATE  COMP  "a2dq7"  SITE  "C16";
 LOCATE  COMP  "a2dq8"  SITE  "D16";\r
 LOCATE  COMP  "a2dq9"  SITE  "B17";\r
 \r
-LOCATE  COMP  "audio_l"  SITE  "H20";\r
-LOCATE  COMP  "audio_r"  SITE  "K18";\r
+LOCATE  COMP  "audio_l"  SITE  "H20"; # out\r
+LOCATE  COMP  "audio_r"  SITE  "K18"; # out\r
 \r
 LOCATE  COMP  "exp_pin_10"  SITE  "J16";\r
 LOCATE  COMP  "exp_pin_11"  SITE  "C13";\r
@@ -57,10 +58,11 @@ IOVUF PORT "orange_led_d8" IO_TYPE=LVCMOS25;
 IOVUF PORT "red_led_d5"    IO_TYPE=LVCMOS25;\r
 IOVUF PORT "yellow_led_d6" IO_TYPE=LVCMOS25;\r
 \r
-LOCATE  COMP  "mhz_16"  SITE  "L20";\r
-LOCATE  COMP  "mhz_96"  SITE  "L17";\r
+LOCATE  COMP  "mhz_16"  SITE  "L20"; # out\r
+LOCATE  COMP  "mhz_96"  SITE  "L17"; # out\r
+\r
+LOCATE  COMP  "res_in"  SITE  "E14"; # in\r
 \r
-LOCATE  COMP  "res_in"  SITE  "E14";\r
 LOCATE  COMP  "rpi_pin_11"  SITE  "D5";\r
 LOCATE  COMP  "rpi_pin_12"  SITE  "G5";\r
 LOCATE  COMP  "rpi_pin_22"  SITE  "E4";\r