From: Dobrica Pavlinusic Date: Tue, 28 Dec 2021 15:44:51 +0000 (+0100) Subject: turn on all leds X-Git-Url: http://git.rot13.org/?p=trilby-hat-fpga;a=commitdiff_plain;h=581839170af0aeffd0334b3eb19334b05f2e1013 turn on all leds --- 581839170af0aeffd0334b3eb19334b05f2e1013 diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..0dee4e6 --- /dev/null +++ b/Makefile @@ -0,0 +1,23 @@ +PROJ:=led +TRELLIS?=/usr/share/trellis + +all: ${PROJ}.bit + +%.json: %.v + yosys -p "synth_ecp5 -json $@" $< + +%_out.config: %.json + nextpnr-ecp5 --json $< --textcfg $@ --45k --package CABGA381 --lpf trilby.lpf + +%.bit: %_out.config + ecppack --svf ${PROJ}.svf $< $@ + +${PROJ}.svf : ${PROJ}.bit + +prog: ${PROJ}.svf + openocd -f openocd/trilby.cfg -c "transport select jtag; init; svf $<; exit" + +clean: + rm -f *.svf *.bit *.config *.json + +.PHONY: prog clean diff --git a/README.md b/README.md new file mode 100644 index 0000000..9faaed2 --- /dev/null +++ b/README.md @@ -0,0 +1,4 @@ +# Trilby HAT ECP5 45k FPGA + +Run `make prog` to load the example to the board. + diff --git a/led.v b/led.v new file mode 100644 index 0000000..00a5405 --- /dev/null +++ b/led.v @@ -0,0 +1,12 @@ +module top( + output green_led_d7, + output orange_led_d8, + output red_led_d5, + output yellow_led_d6 + ); + assign green_led_d7 = 1; + assign orange_led_d8 = 1; + assign red_led_d5 = 1; + assign yellow_led_d6 = 1; + +endmodule diff --git a/openocd/trilby.cfg b/openocd/trilby.cfg new file mode 100644 index 0000000..c6acafb --- /dev/null +++ b/openocd/trilby.cfg @@ -0,0 +1,29 @@ +# +# Config for Trilby HAT with ecp5 45k using Raspberry Pi's expansion header +# +# This is best used with a fast enough buffer but also +# is suitable for direct connection if the target voltage +# matches RPi's 3.3V and the cable is short enough. +# +# Do not forget the GND connection, pin 6 of the expansion header. +# + +adapter driver bcm2835gpio + +bcm2835gpio_peripheral_base 0x3F000000 + +# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET +# These depend on system clock, calibrated for stock 700MHz +# bcm2835gpio_speed SPEED_COEFF SPEED_OFFSET +bcm2835gpio_speed_coeffs 146203 36 + +# Each of the JTAG lines need a gpio number set: tck tms tdi tdo +bcm2835gpio_jtag_nums 23 27 22 24 + +reset_config none + +adapter speed 50 +transport select jtag + +# Trilby HAT +jtag newtap ecp5 tap -irlen 8 -expected-id 0x41112043 diff --git a/trilby.lpf b/trilby.lpf new file mode 100644 index 0000000..535e9f8 --- /dev/null +++ b/trilby.lpf @@ -0,0 +1,102 @@ +# created based on https://github.com/danderson/ulxs/blob/main/lpf.md +# and output files + +# PART TYPE: LFE5U-45F +# Performance Grade: 6 +# PACKAGE: CABGA381 + +#SYSCONFIG SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF DONE_EX=OFF DONE_OD=ON DONE_PULL=ON MCCLK_FREQ=2.4 TRANSFR=OFF CONFIG_IOVOLTAGE=2.5 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF CONFIG_MODE=JTAG ; + +LOCATE COMP "AGC_A" SITE "E8"; + +LOCATE COMP "clk" SITE "U16"; # CLK 24Mhz TCXO +IOBUF PORT "clk" IO_TYPE=LVCMOS25; # ? 33? + +LOCATE COMP "a2dq10" SITE "C17"; +LOCATE COMP "a2dq11" SITE "A18"; +LOCATE COMP "a2dq12" SITE "A19"; +LOCATE COMP "a2dq13" SITE "B19"; +LOCATE COMP "a2dq2" SITE "B12"; +LOCATE COMP "a2dq3" SITE "D15"; +LOCATE COMP "a2dq4" SITE "C15"; +LOCATE COMP "a2dq5" SITE "B15"; +LOCATE COMP "a2dq6" SITE "E15"; +LOCATE COMP "a2dq7" SITE "C16"; +LOCATE COMP "a2dq8" SITE "D16"; +LOCATE COMP "a2dq9" SITE "B17"; + +LOCATE COMP "audio_l" SITE "H20"; +LOCATE COMP "audio_r" SITE "K18"; + +LOCATE COMP "exp_pin_10" SITE "J16"; +LOCATE COMP "exp_pin_11" SITE "C13"; +LOCATE COMP "exp_pin_12" SITE "E19"; +LOCATE COMP "exp_pin_13" SITE "D13"; +LOCATE COMP "exp_pin_14" SITE "E20"; +LOCATE COMP "exp_pin_15" SITE "E13"; +LOCATE COMP "exp_pin_16" SITE "F19"; +LOCATE COMP "exp_pin_17" SITE "A14"; +LOCATE COMP "exp_pin_18" SITE "F20"; +LOCATE COMP "exp_pin_19" SITE "C14"; +LOCATE COMP "exp_pin_21" SITE "D14"; +LOCATE COMP "exp_pin_3" SITE "E12"; +LOCATE COMP "exp_pin_4" SITE "H18"; +LOCATE COMP "exp_pin_5" SITE "A12"; +LOCATE COMP "exp_pin_6" SITE "H17"; +LOCATE COMP "exp_pin_7" SITE "A13"; +LOCATE COMP "exp_pin_8" SITE "J17"; +LOCATE COMP "exp_pin_9" SITE "B13"; + +LOCATE COMP "green_led_d7" SITE "G16"; +LOCATE COMP "orange_led_d8" SITE "H16"; +LOCATE COMP "red_led_d5" SITE "E18"; +LOCATE COMP "yellow_led_d6" SITE "F18"; + +IOVUF PORT "green_led_d7" IO_TYPE=LVCMOS25; +IOVUF PORT "orange_led_d8" IO_TYPE=LVCMOS25; +IOVUF PORT "red_led_d5" IO_TYPE=LVCMOS25; +IOVUF PORT "yellow_led_d6" IO_TYPE=LVCMOS25; + +LOCATE COMP "mhz_16" SITE "L20"; +LOCATE COMP "mhz_96" SITE "L17"; + +LOCATE COMP "res_in" SITE "E14"; +LOCATE COMP "rpi_pin_11" SITE "D5"; +LOCATE COMP "rpi_pin_12" SITE "G5"; +LOCATE COMP "rpi_pin_22" SITE "E4"; +LOCATE COMP "rpi_pin_29" SITE "E3"; +LOCATE COMP "rpi_pin_31" SITE "E5"; +LOCATE COMP "rpi_pin_32" SITE "D1"; +LOCATE COMP "rpi_pin_33" SITE "F5"; +LOCATE COMP "rpi_pin_35" SITE "A2"; +LOCATE COMP "rpi_pin_36" SITE "C1"; +LOCATE COMP "rpi_pin_37" SITE "B1"; +LOCATE COMP "rpi_pin_38" SITE "C2"; +LOCATE COMP "rpi_pin_40" SITE "B2"; + +LOCATE COMP "rtc_mfp" SITE "E2"; +LOCATE COMP "rtc_scl" SITE "B3"; +LOCATE COMP "rtc_sda" SITE "A3"; + +LOCATE COMP "spi_cs0" SITE "E1"; +LOCATE COMP "spi_cs1" SITE "D2"; +LOCATE COMP "spi_miso" SITE "D3"; +LOCATE COMP "spi_mosi" SITE "C3"; +LOCATE COMP "spi_sclk" SITE "F4"; + +LOCATE COMP "tuner_hf" SITE "D8"; +LOCATE COMP "tuner_scl" SITE "C6"; +LOCATE COMP "tuner_sda" SITE "C7"; + +LOCATE COMP "uart_rx" SITE "G3"; +LOCATE COMP "uart_tx" SITE "H3"; + +LOCATE COMP "unused" SITE "B11"; + +#PLL +LOCATE COMP "I518/pll_24_to_96_inst/PLLInst_0" SITE "PLL_BR0" ; + +#FREQUENCY NET "N_355" 16.000000 MHz ; +#FREQUENCY NET "clkfast" 96.000000 MHz ; +#FREQUENCY NET "clk24" 24.000000 MHz ; +#FREQUENCY NET "N_810" 24.000000 MHz ;