we need read_verilog instead of read
[trilby-hat-fpga] / i2c.v
2022-01-06 Dobrica Pavlinusicuse SPI slave
2021-12-30 Dobrica Pavlinusicadd FPGA generated clocks mhz_16, mhz_96
2021-12-30 Dobrica Pavlinusici2c passthru bridge from rpi to tuner