From 302c67c98a30def10b8b8845c6f820d9e8da130b Mon Sep 17 00:00:00 2001
From: Dobrica Pavlinusic <dpavlin@rot13.org>
Date: Fri, 21 Jan 2022 12:44:55 +0100
Subject: [PATCH] we need read_verilog instead of read

Otherwise, all modules in recent yosys become abstract, and
optimized out
---
 Makefile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 34477b7..ed75e6e 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@ TRELLIS?=/usr/share/trellis
 all: ${PROJ}.bit
 
 %.json: %.v
-	yosys -p "synth_ecp5 -json $@" $<
+	yosys -p "read_verilog ${PROJ}.v ; synth_ecp5 ; write_json $@" -E .$(basename $@).d $<
 
 %_out.config: %.json
 	nextpnr-ecp5 --json $< --textcfg $@ --45k --package CABGA381 --lpf trilby.lpf
@@ -22,3 +22,4 @@ clean:
 	rm -f *.svf *.bit *.config *.json
 
 .PHONY: prog clean
+-include .*.d
-- 
2.20.1