From 2d59bb8882c8405bc400614a0db8b59db5a5fcc4 Mon Sep 17 00:00:00 2001 From: Dobrica Pavlinusic Date: Mon, 30 Jul 2007 00:31:46 -0500 Subject: [PATCH] initial try to make DSM G-600 support --- Makefile | 15 +++- board/sandpoint/config.mk | 8 ++- board/sandpoint/early_init.S | 20 ++++++ board/sandpoint/flash.c | 2 + board/sandpoint/sandpoint.c | 10 ++- common/cmd_bootm.c | 1 + cpu/mpc824x/cpu.c | 2 + cpu/mpc824x/cpu_init.c | 1 + include/asm-ppc/arch | 2 +- include/config.h | 5 +- include/config.mk | 4 +- include/configs/Sandpoint8245.h | 122 +++++++++++++++++--------------- 12 files changed, 121 insertions(+), 71 deletions(-) diff --git a/Makefile b/Makefile index daa6f04..7470ff0 100644 --- a/Makefile +++ b/Makefile @@ -54,7 +54,7 @@ ifeq ($(HOSTARCH),ppc) CROSS_COMPILE = else ifeq ($(ARCH),ppc) -CROSS_COMPILE = ppc_6xx- +CROSS_COMPILE = powerpc-linux- endif ifeq ($(ARCH),arm) CROSS_COMPILE = arm-linux- @@ -130,7 +130,6 @@ PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) - # The "tools" are needed early, so put this first # Don't include stuff already done in $(LIBS) SUBDIRS = tools \ - examples \ post \ post/cpu .PHONY : $(SUBDIRS) @@ -176,6 +175,9 @@ linkstation_HDLAN: include/config.h @make all @mv u-boot.bin u-boot-hd.flash.bin +dsmg600: include/config.h + @make all + u-boot.hex: u-boot $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ @@ -199,7 +201,7 @@ u-boot: depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT) UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ $(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \ --start-group $(LIBS) --end-group $(PLATFORM_LIBS) \ - -Map u-boot.map -o u-boot + -o u-boot $(LIBS): $(MAKE) -C `dirname $@` @@ -1042,6 +1044,13 @@ linkstation_HDLAN_config: mrproper ./mkconfig -a linkstation ppc mpc824x linkstation ; \ echo "LinkStation HDLAN -- ROM BUILD ..." +dsmg600_ram_config: mrproper + @>include/config.h ; \ + echo "/* DSM-G600 RAM */" >>include/config.h ; \ + echo "TEXT_BASE = 0x01F00000" >board/sandpoint/config.tmp ; \ + ./mkconfig -a Sandpoint8245 ppc mpc824x sandpoint ; \ + echo "DSM G-600 -- RAM BUILD ..." + MOUSSE_config: unconfig @./mkconfig $(@:_config=) ppc mpc824x mousse diff --git a/board/sandpoint/config.mk b/board/sandpoint/config.mk index b3f65eb..e16d7bc 100644 --- a/board/sandpoint/config.mk +++ b/board/sandpoint/config.mk @@ -25,7 +25,11 @@ # Sandpoint boards # -#TEXT_BASE = 0x00090000 -TEXT_BASE = 0xFFF00000 +ifndef TEXT_BASE +# For flash image - all models +#TEXT_BASE = 0xFFF00000 +# For RAM image +TEXT_BASE = 0x01F00000 +endif PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/sandpoint/early_init.S b/board/sandpoint/early_init.S index 07dafb7..8b3e791 100644 --- a/board/sandpoint/early_init.S +++ b/board/sandpoint/early_init.S @@ -37,6 +37,21 @@ #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) #endif + +#define UART1 0xfc004500 +#define UART1_IER 0xfc004501 +#define UART1_FCR 0xfc004502 +#define UART1_LCR 0xfc004503 +#define UART1_DCR 0xfc004511 + +#define WM8(address,data) \ + lis r3, address@h; \ + ori r3, r3, address@l; \ + li r4, data; \ + stb r4, 0(r3); \ + sync; \ + isync; + .text /* Values to program into memory controller registers */ @@ -105,6 +120,10 @@ tbl: .long MCCR1, MCCR1VAL early_init_f: mflr r10 + WM8(0xfc004500,0x44); + +#if 0 + /* basic memory controller configuration */ lis r3, CONFIG_ADDR_HIGH lis r4, CONFIG_DATA_HIGH @@ -147,6 +166,7 @@ delay: bdnz delay /* set up stack pointer */ lis r1, CFG_INIT_SP_OFFSET@h ori r1, r1, CFG_INIT_SP_OFFSET@l +#endif mtlr r10 blr diff --git a/board/sandpoint/flash.c b/board/sandpoint/flash.c index a9f73ff..fdb724e 100644 --- a/board/sandpoint/flash.c +++ b/board/sandpoint/flash.c @@ -152,12 +152,14 @@ flash_init(void) } /* Enable writes to Sandpoint flash */ +#if 0 { register unsigned char temp; CONFIG_READ_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); temp &= ~0x20; /* clear BIOSWP bit */ CONFIG_WRITE_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); } +#endif for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) { diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c index d3445bd..1058164 100644 --- a/board/sandpoint/sandpoint.c +++ b/board/sandpoint/sandpoint.c @@ -59,6 +59,7 @@ long int initdram (int board_type) size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); +#if 0 new_bank0_end = size - 1; mear1 = mpc824x_mpc107_getreg(MEAR1); emear1 = mpc824x_mpc107_getreg(EMEAR1); @@ -68,15 +69,18 @@ long int initdram (int board_type) ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); mpc824x_mpc107_setreg(MEAR1, mear1); mpc824x_mpc107_setreg(EMEAR1, emear1); +#endif return (size); } + /* * Initialize PCI Devices, report devices found. */ #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_sandpoint_config_table[] = { +#if 0 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, PCI_ENET0_MEMADDR, @@ -86,8 +90,8 @@ static struct pci_config_table pci_sandpoint_config_table[] = { PCI_ENET1_MEMADDR, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, { } -}; #endif +}; struct pci_controller hose = { #ifndef CONFIG_PCI_PNP @@ -95,7 +99,9 @@ struct pci_controller hose = { #endif }; +#endif void pci_init_board(void) { - pci_mpc824x_init(&hose); + //pci_mpc824x_init(&hose); } + diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 2c7cdef..9a18b05 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -193,6 +193,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr, NULL, verify); return 1; /* Only returns on error */ #endif +// FIXME boot_kernel!! { puts ("Bad Magic Number\n"); SHOW_BOOT_PROGRESS (-1); diff --git a/cpu/mpc824x/cpu.c b/cpu/mpc824x/cpu.c index 4effb12..c1ca0a5 100644 --- a/cpu/mpc824x/cpu.c +++ b/cpu/mpc824x/cpu.c @@ -95,6 +95,7 @@ int checkdcache (void) #ifndef CONFIG_LINKSTATION int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { +#if 0 ulong msr, addr; /* Interrupts and MMU off */ @@ -124,6 +125,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif ((void (*)(void)) addr) (); return 1; +#endif } #endif diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c index 7871031..91e3e43 100644 --- a/cpu/mpc824x/cpu_init.c +++ b/cpu/mpc824x/cpu_init.c @@ -294,6 +294,7 @@ cpu_init_f (void) #if defined(MIOCR2) && defined(CFG_SDRAM_DSCD) CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD); /* change memory input */ #endif /* setup & hold time */ +// CONFIG_WRITE_BYTE(PMCR2, CFG_PCI_HOLD_DEL); //jack20050526+ CONFIG_WRITE_BYTE(MBER, CFG_BANK0_ENABLE | diff --git a/include/asm-ppc/arch b/include/asm-ppc/arch index b99db9a..a2f45b9 120000 --- a/include/asm-ppc/arch +++ b/include/asm-ppc/arch @@ -1 +1 @@ -arch-mpc8260 \ No newline at end of file +arch-mpc824x \ No newline at end of file diff --git a/include/config.h b/include/config.h index 4afde76..839b45a 100644 --- a/include/config.h +++ b/include/config.h @@ -1,5 +1,4 @@ -#define CONFIG_ADSTYPE CFG_PQ2FADS -#define CONFIG_8260_CLKIN 66000000 +/* DSM-G600 RAM */ /* Automatically generated - do not edit */ -#include +#include diff --git a/include/config.mk b/include/config.mk index 58834cf..c501a9f 100644 --- a/include/config.mk +++ b/include/config.mk @@ -1,3 +1,3 @@ ARCH = ppc -CPU = mpc8260 -BOARD = mpc8260ads +CPU = mpc824x +BOARD = sandpoint diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h index d42bd69..06f1cd6 100644 --- a/include/configs/Sandpoint8245.h +++ b/include/configs/Sandpoint8245.h @@ -45,24 +45,30 @@ #undef USE_DINK32 #endif -#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ +#define CONFIG_CONS_INDEX 1 /* set to '3' for on-chip DUART */ #define CONFIG_BAUDRATE 9600 #define CONFIG_DRAM_SPEED 100 /* MHz */ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) +#define CONFIG_COMMANDS ( \ + CFG_CMD_BDI | \ + CFG_CMD_FLASH | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_RUN | \ + CFG_CMD_ECHO | \ + CFG_CMD_PCI ) + +#undef CONFIG_VIDEO /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include +/* 0x00 for 66 MHz, 0x40 for 33 MHz */ +#define CFG_PCI_HOLD_DEL 0x40 /* * Miscellaneous configurable options @@ -82,18 +88,20 @@ */ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NATSEMI -#define CONFIG_NS8382X - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 +/*----------------------------------------------------------------------- + * Change TEXT_BASE in bord/linkstation/config.mk to get a RAM build + * + * RAM based builds are for testing purposes. A Linux module, uloader.o, + * exists to load U-Boot and pass control to it + * + * Always do "make clean" after changing the build type + */ +#if CFG_MONITOR_BASE < CFG_FLASH_BASE +#define CFG_RAMBOOT +#warn CFG_RAMBOOT +#endif /*----------------------------------------------------------------------- @@ -129,29 +137,36 @@ #endif -#define CFG_FLASH_BASE 0xFFF00000 +#define CFG_FLASH_BASE 0xFFC00000 #if 0 #define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ #else -#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ +#define CFG_FLASH_SIZE (4 * 1024 * 1024) /* 4MByte flash */ #endif + +#if 0 #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ +#endif + +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_NOWHERE +#define CFG_ENV_SIZE 0x20000 #define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ #define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ #define CFG_EUMB_ADDR 0xFC000000 - +/* #define CFG_ISA_MEM 0xFD000000 #define CFG_ISA_IO 0xFE000000 - -#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ -#define CFG_FLASH_RANGE_SIZE 0x01000000 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ +*/ +#define CFG_FLASH_RANGE_BASE 0xFFC00000 /* flash memory address range */ +#define CFG_FLASH_RANGE_SIZE 0x00400000 +#define FLASH_BASE0_PRELIM 0xFFC00000 /* sandpoint flash */ #define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ /* @@ -161,10 +176,12 @@ * If the software driver is chosen, there are some additional * configuration items that the driver uses to drive the port pins. */ +#if 0 #define CONFIG_HARD_I2C 1 /* To enable I2C support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +#endif #ifdef CONFIG_SOFT_I2C #error "Soft I2C is not configured properly. Please review!" @@ -179,19 +196,21 @@ #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ #endif /* CONFIG_SOFT_I2C */ +#if 0 #define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ #define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#endif #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } +#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM } /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ - +#if 0 #define CFG_WINBOND_83C553 1 /*has a winbond bridge */ #define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ @@ -221,6 +240,8 @@ #define CFG_NS87308_CS2_BASE 0x0074 #define CFG_NS87308_CS2_CONF 0x30 +#endif + /* * NS16550 Configuration */ @@ -229,16 +250,10 @@ #define CFG_NS16550_REG_SIZE 1 -#if (CONFIG_CONS_INDEX > 2) -#define CFG_NS16550_CLK CONFIG_DRAM_SPEED*1000000 -#else -#define CFG_NS16550_CLK 1843200 -#endif +#define CFG_NS16550_CLK 100000000 -#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) -#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) -#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500) -#define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600) +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) /* * Low Level Configuration Settings @@ -246,10 +261,10 @@ * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +#define CONFIG_SYS_CLK_FREQ 100000000 /* external frequency to pll */ -#define CFG_ROMNAL 7 /*rom/flash next access time */ -#define CFG_ROMFAL 11 /*rom/flash access time */ +#define CFG_ROMNAL 8 /*rom/flash next access time */ +#define CFG_ROMFAL 13 /*rom/flash access time */ #define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */ @@ -258,7 +273,7 @@ #define CFG_REFREC 8 /* Refresh to activate interval */ #define CFG_RDLAT 4 /* data latency from read command */ #define CFG_PRETOACT 3 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTTOPRE 6 /* Activate to Precharge interval */ #define CFG_ACTORW 3 /* Activate to R/W */ #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ @@ -353,8 +368,8 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ @@ -367,6 +382,10 @@ # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif +/*----------------------------------------------------------------------- + * Partitions and file system + */ +#define CONFIG_DOS_PARTITION /* * Internal Definitions @@ -376,17 +395,4 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - #endif /* __CONFIG_H */ -- 2.20.1