#define HID0_ICE (1<<15) /* Instruction Cache Enable */
#define HID0_DCE (1<<14) /* Data Cache Enable */
+
+#define UART1 0xfc004500
+#define UART1_IER 0xfc004501
+#define UART1_FCR 0xfc004502
+#define UART1_LCR 0xfc004503
+#define UART1_DCR 0xfc004511
+
+#define WM8(address,data) \
+ lis r3, address@h; \
+ ori r3, r3, address@l; \
+ li r4, data; \
+ stb r4, 0(r3); \
+ sync; \
+ isync;
+
+
.section ".text"
.globl load_uboot
mr r30,r4 /* pa_uboot_buf */
mr r29,r5 /* load_address */
+ /* Init UART for AVR */
+ WM8(UART1_LCR,0x00) /* clear LCR */
+ WM8(UART1_IER,0x00) /* disable interrupt */
+ WM8(UART1_LCR,0x80) /* set LCR[DLAB] bit */
+ WM8(UART1_DCR,0x01) /* set DUART mode */
+ WM8(UART1, 0x8B) /* set DLL(baudrate 9600bps, 100MHz) */
+ WM8(UART1_IER,0x02) /* set DLM(baudrate 9600bps, 100MHz) */
+ WM8(UART1_LCR,0x03) /* set 8data, 1stop, non parity */
+ WM8(UART1, 0x00) /* clear MCR */
+ WM8(UART1_FCR,0x07) /* clear & enable FIFO */
+
+ WM8(0xfc004500,0x41);
+
/* disable interrupts */
mfmsr r0
rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
mr r4,r29 /* load address */
addi r30,r30,4 /* skip size */
-2: li r0,1024
+2:
+
+ WM8(0xfc004500,0x42);
+ li r0,1024
lwz r9,0(r30)
mtctr r0
cmpwi r0,0
bne 2b
+ WM8(0xfc004500,0x43);
/* jump to uboot */
lis r1,0x100 /* put stack at 16M */
li r3,0
mtlr r9
blr
+ WM8(0xfc004500,0x44);
disable_cache:
li r2,1024 /* flush 16K cache */
mtctr r2
return NOTIFY_DONE;
}
- printk(KERN_INFO "uloader module booting u-boot\n");
-
+ //printk(KERN_INFO "load_uboot(%8x,%8x,%8x)\n",va2pa(load_uboot), va2pa(uboot_buf), laddr);
+ printk(KERN_INFO "A");
load_uboot(va2pa(load_uboot), va2pa(uboot_buf), laddr);
return NOTIFY_DONE; /* This should never be reached */