library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;

entity dac is
    Port ( clk : in STD_LOGIC;
	        dac_a : out  STD_LOGIC_VECTOR (4 downto 0);
           dac_b : out  STD_LOGIC_VECTOR (4 downto 0);

          test_port : out  STD_LOGIC_VECTOR (14 downto 0));
end dac;


architecture RTL of dac is
signal counter : STD_LOGIC_VECTOR (20 downto 0);
begin
  test: process (clk) is
  begin
    if (rising_edge(clk)) then
      counter <= counter + '1';

		-- 5 bit R2R DAC 0-3.3V
      dac_a <= counter (4 downto 0);
      dac_b <= counter (4 downto 0);

		-- other pins without assigment
--      test_port <= counter (14 downto 0); -- four ports so that

--      test_port_d <= counter (20 downto 13); -- all pins are tested
--	   test_pin <= counter (0);              -- test single bit left over
    end if;
  end process test;
end RTL;