6 "at91sam7": {0x000000: (0x100000, "Flash before remap, SRAM after remap"),
7 0x100000: (0x100000, "Internal Flash"),
8 0x200000: (0x100000, "Internal SRAM"),
10 "at91r40008":{0x000000: (0x100000, "Flash before remap, SRAM after remap"),
11 0x100000: (0x100000, "Internal Flash"),
12 0x200000: (0x100000, "Internal SRAM"),
13 0x300000: (0x100000, "Internal SRAM - pre-remap"),
14 0x400000: (0xfc000000-0x400000, "External Bus Interface Addressing"),
18 # gratuitously leveraged from atmel's Flash_uploader demo app
20 ( WRITE, 0xFFE00000, 0x01002529 ), #* Write EBI_CSR0
21 ( WRITE, 0xFFE00004, 0x02002121 ), #* Write EBI_CSR1
22 ( WRITE, 0xFFE00020, 0x00000001 ), #* Remap Command
23 ( WRITE, 0xFFE00024, 0x00000006 ) #* Memory Control Register
27 ( WRITE, 0xFFE00000, 0x01002539 ), #* Write EBI_CSR0 0x01002539
28 ( WRITE, 0xFFE00020, 0x00000001 ), #* Remap Command
29 ( WRITE, 0xFFE00024, 0x00000006 ) #* Memory Control Register
33 ( WRITE, 0xFFE00000, 0x01002529 ), #* Write EBI_CSR0
34 ( WRITE, 0xFFE00004, 0x02002121 ), #* Write EBI_CSR1
35 ( WRITE, 0xFFE00020, 0x00000001 ), #* Remap Command
36 ( WRITE, 0xFFE00024, 0x00000006 ) #* Memory Control Register
40 ( WRITE, 0xFFE00000, 0x01002529 ), #* Write EBI_CSR0
41 ( WRITE, 0xFFE00004, 0x02002121 ), #* Write EBI_CSR1
42 ( WRITE, 0xFFE00020, 0x00000001 ), #* Remap Command
43 ( WRITE, 0xFFE00024, 0x00000006 ) #* Memory Control Register
47 ( WRITE, 0xFFE00000, 0x01002529 ), #* Write EBI_CSR0
48 ( WRITE, 0xFFE00004, 0x02002121 ), #* Write EBI_CSR1
49 ( WRITE, 0xFFE00020, 0x00000001 ), #* Remap Command
50 ( WRITE, 0xFFE00024, 0x00000006 ) #* Memory Control Register
54 #* Disable external watchdog assertion
55 ( WRITE, 0xFFFF8008, 0x00000000 ), #* ST_WMR
57 #* Set up the Clock frequency to run at 32,768 MHz with PLLB
58 ( WRITE, 0xFFFF4020, 0xC503E708 ), #* PMC_CGMR
60 #* Reading the PMC Status register to detect when the PLLB is stabilized
61 ( POLL, 0xFFFF4030, 0x00000001 ), #* PMC_SR
63 #* Commuting from Slow Clock to PLLB
64 ( WRITE, 0xFFFF4020, 0xC503E798 ) #* PMC_CGMR
68 #* Enable the main oscillator (16Mhz) / MOSCEN = 1, OSCOUNT = 47 (1.4ms/30µs)
69 ( WRITE, 0xFFFF4020, 0x002F0002 ), #* APMC_CGMR
71 #* Wait for Main oscillator stabilization. Wait for APMC_MOSCS Bit in APMC_SR equals 1
72 ( POLL, 0xFFFF4030, 0x00000001 ), #* APMC_SR
74 #* Commuting from Slow Clock to Main Oscillator (32K to 16Mhz)
75 ( WRITE, 0xFFFF4020, 0x002F4002 ), #* APMC_CGMR
77 #* Setup the PLL / MUL = 1, PLLCOUNT = 3, CSS = 1
78 ( WRITE, 0xFFFF4020, 0x032F4102 ), #* APMC_CGMR
80 #* Wait for the PLL is stabilized. Wait for APMC_PLL_LOCK Bit in APMC_SR equals 1
81 ( POLL, 0xFFFF4030, 0x00000002 ), #* APMC_SR
83 #* Commuting from 16Mhz to PLL @ 32MHz / CSS = 2, MUL = 1
84 ( WRITE, 0xFFFF4020, 0x032F8102 ) #* APMC_CGMR
92 { EB40_EBI_desc, sizeof(EB40_EBI_desc)/sizeof(Instr) },
94 {(u_int *)FLASH_LV_PRG, 0x7D0, 0x20 }, //* Flash algo
95 {(u_int *)0x0101C000, 0x7D0, 0x20 }, //* Flash identify
96 {(u_int *)0x01020000, 0x800, 0x0 }, //* boot 2KB
97 {(u_int *)0x01030000, 0xCD00, 0x2000 }, //* angel 51KB
98 {(u_int *)0x01028000, 0x1800, 0x00010000 }, //* appli 6KB
99 { NULL, 0, 0 } //* Mirror
104 { EB40A_EBI_desc, sizeof(EB40A_EBI_desc)/sizeof(Instr) },
106 {(u_int *)FLASH_BV_PRG, 0x7D0, 0x20 }, //* Flash algo
107 {(u_int *)0x0101E000, 0x400, 0x20 }, //* Flash identify
108 {(u_int *)0x01040000, 0x2800, 0x01000000 }, //* boot 10KB
109 {(u_int *)0x01050000, 0xCD00, 0x01006000 }, //* angel 51KB
110 {(u_int *)0x01048000, 0x1800, 0x01100000 }, //* appli 4KB
111 {(u_int *)0x01000000, 0x200000 , 0x01000000 } //* Mirror
115 { EB42_PLL_desc, sizeof(EB42_PLL_desc)/sizeof(Instr) },
116 { EB42_EBI_desc, sizeof(EB42_EBI_desc)/sizeof(Instr) },
118 {(u_int *)FLASH_BV_PRG, 0x7D0, 0x20 }, //* Flash algo
119 {(u_int *)0x0101E000, 0x400, 0x20 }, //* Flash identify
120 {(u_int *)0x01060000, 0x3400, 0x01000000 }, //* boot 13KB
121 {(u_int *)0x01070000, 0xCD00, 0x01006000 }, //* angel 51KB
122 {(u_int *)0x01068000, 0x1800, 0x01100000 }, //* appli 4KB 0x1170000 0x1100000
123 { NULL, 0, 0 } //* Mirror
127 { EB55_PLL_desc, sizeof(EB55_PLL_desc)/sizeof(Instr) },
128 { EB55_EBI_desc, sizeof(EB55_EBI_desc)/sizeof(Instr) },
130 {(u_int *)FLASH_BV_PRG, 0x7D0, 0x20 }, //* Flash algo
131 {(u_int *)0x0101E000, 0x400, 0x20 }, //* Flash identify
132 {(u_int *)0x01080000, 0x4C00, 0x01000000 }, //* boot 19KB
133 {(u_int *)0x01090000, 0xCD00, 0x01006000 }, //* angel 51KB
134 {(u_int *)0x01088000, 0x1800, 0x01100000 }, //* appli 4KB
135 { NULL, 0, 0 } //* Mirror
140 { EB63_EBI_desc, sizeof(EB63_EBI_desc)/sizeof(Instr) },
142 {(u_int *)FLASH_BV_PRG, 0x7D0, 0x20 }, //* Flash algo
143 {(u_int *)0x0101E000, 0x400, 0x20 }, //* Flash identify
144 {(u_int *)0x010A0000, 0x2800, 0x01000000 }, //* boot 10KB
145 {(u_int *)0x010B0000, 0xCD00, 0x01004000 }, //* angel 51KB
146 {(u_int *)0x010A8000, 0x1800, 0x01100000 }, //* appli 4KB
147 { NULL, 0, 0 } //* Mirror