3 This library helps interface with USARTs on Atmel microcontrollers. The library has been modeled after the AT91X40 series (1354D-ATARM-08/02). AT91SAM7 has also been thrown in a little.
6 USART0_BASE = 0xfffd0000
7 USART1_BASE = 0xfffcc000
10 US_MR_OFF = 0x04 # R/w
11 US_IER_OFF = 0x08 # wO
12 US_IDR_OFF = 0x0c # wO
14 US_IMR_OFF = 0x10 # RO
15 US_CSR_OFF = 0x14 # RO
16 US_RHR_OFF = 0x18 # RO
17 US_THR_OFF = 0x1c # wO
19 US_BRGR_OFF = 0x20 # R/w
20 US_RTOR_OFF = 0x24 # R/w
21 US_TTGR_OFF = 0x28 # R/w
23 US_RPR_OFF = 0x30 # R/w - AT91X40
24 US_RCR_OFF = 0x34 # R/w - AT91X40
25 US_TPR_OFF = 0x38 # R/w - AT91X40
26 US_TCR_OFF = 0x3c # R/w - AT91X40
28 US_FIDI_OFF = 0x40 # R/w - AT91SAM7
29 US_NER_OFF = 0x44 # RO - AT91SAM7
30 US_IF_OFF = 0x4c # R/w - AT91SAM7
71 CSR_TIMEOUT:"TIMEOUT",
72 CSR_TXEMPTY:"TXEMPTY",
92 def __init__(self, arm7_gf_client, base_addr=USART0_BASE):
93 self.client = arm7_gf_client
94 self.base_addr = base_addr
96 def setControlReg(self, cr):
97 """ only integers, please """
98 self.client.writeMem(self.base + US_CR_OFF, [cr])
100 return self.client.readMem(self.base + US_MR_OFF, 1)
101 def setModeReg(self, mr):
102 return self.client.writeMem(self.base + US_MR_OFF, [mr])
103 def interruptEnable(self, mask=0):
104 self.client.writeMem(self.base + US_IER_OFF, [mask])
105 def interruptDisable(self, mask=0):
106 self.client.writeMem(self.base + US_IDR_OFF, [mask])
108 def getInterruptMask(self):
109 return self.client.readMem(self.base + US_IMR_OFF,1)
110 def getChannelStatus(self):
111 return self.client.readMem(self.base + US_CSR_OFF,1)
112 def getRecvHoldReg(self):
113 return self.client.readMem(self.base + US_RHR_OFF,1)
114 def setXmitHoldReg(self, char):
115 num, = struct.unpack("B",char)
116 self.client.writeMem(self.base + US_THR_OFF,[num])
118 def getBaudRateGenReg(self):
119 return self.client.readMem(self.base + US_BRGR_OFF,1)
120 def setBaudRateGenReg(self, brgr):
121 self.client.writeMem(self.base + US_BRGR_OFF,[brgr])
122 def getRecvTOReg(self):
123 return self.client.readMem(self.base + US_RTOR_OFF,1)
124 def setRecvTOReg(self, rtor):
125 self.client.writeMem(self.base + US_RTOR_OFF,[rtor])
126 def getXmitTOReg(self):
127 return self.client.readMem(self.base + US_TTOR_OFF,1)
128 def setXmitTOReg(self, ttor):
129 self.client.writeMem(self.base + US_TTOR_OFF,[ttor])
131 def getRecvPtrReg(self):
132 return self.client.readMem(self.base + US_RPR_OFF,1)
133 def setRecvPtrReg(self, rpr):
134 self.client.writeMem(self.base + US_RPR_OFF,[rpr])
135 def getRecvCtrReg(self):
136 return self.client.readMem(self.base + US_RCR_OFF,1)
137 def setRecvCtrReg(self, cpr):
138 self.client.writeMem(self.base + US_RCR_OFF,[rcr])
139 def getXmitPtrReg(self):
140 return self.client.readMem(self.base + US_TPR_OFF,1)
141 def setXmitPtrReg(self, tpr):
142 self.client.writeMem(self.base + US_TPR_OFF,[tpr])
143 def getXmitCtrReg(self):
144 return self.client.readMem(self.base + US_TCR_OFF,1)
145 def setXmitCtrReg(self, cpr):
146 self.client.writeMem(self.base + US_TCR_OFF,[tcr])
148 def crResetRecv(self):
149 self.setControlReg(CR_RSTRX)
150 def crResetXmit(self):
151 self.setControlReg(CR_RSTTX)
152 def crEnableRecv(self):
153 self.setControlReg(CR_RXEN)
154 def crDisableRecv(self):
155 self.setControlReg(CR_RXDIS)
156 def crEnableXmit(self):
157 self.setControlReg(CR_TXEN)
158 def crDisableXmit(self):
159 self.setControlReg(CR_TXDIS)
160 def crResetStatus(self):
161 self.setControlReg(CR_RSTSTA)
162 def crStartBreak(self):
163 self.setControlReg(CR_STTBRK)
164 def crStopBreak(self):
165 self.setControlReg(CR_STPBRK)
166 def crStartTimeout(self):
167 self.setControlReg(CR_STTTO)
168 def crSendAddress(self):
169 self.setControlReg(CR_SENDA)
170 def crSendBreak(self):
172 while (timeout > 0 and self.getChannelStatus() & CSR_TXRDY):
176 while (timeout > 0 and self.getChannelStatus() & CSR_TXRDY):
180 def mrGetModeParts(self):
181 mode = self.getMode()
182 usart_mode = mode & 0xf
183 usclks = ((mode>>4) & 3)
184 chrl = ((mode>>6) & 3) + 5
185 sync = ((mode>>8) & 1)
186 par = ((mode>>9) & 7)
187 nbstop = ((mode>>12)& 3)
188 chmode = ((mode>>14)& 3)
189 mode9 = ((mode>>17)& 1)
190 cklo = ((mode>>18)& 1)
191 return (usclks,chrl,sync,par,nbstop,chmode,mode9,cklo)
192 def mrReprUsartMode(self):
193 return ("normal","rs485","hwhandshake","modem","iso7816/t=0",
194 "reserved","iso7816/t=1","reserved","irda","reserved",
195 "reserved","reserved","reserved","reserved","reserved",
196 "reserved","reserved",)[self.mrGetModeParts()[0]]
197 def mrReprSelectedClock(self):
198 return MR_USCLKS_INTERP[self.mrGetModeParts()[1]]
199 def mrReprParity(self):
200 return ("even","odd","forced-0","forced-1","None","None","Multidrop")[self.mrGetModeParts()[4]]
201 def mrReprStopBits(self):
202 return ("1","1.5","2","reserved")[self.mrGetModeParts()[5]]
203 def mrReprChannelMode(self):
204 return ("normal","auto-echo","local-loopback","remote-loopback")[self.mrGetModeParts()[5]]
206 def csrReprStatus(self):
207 csr = self.getControlStatus()
209 for bit in xrange(10):
212 output.append(INTERRUPTS[b])
213 return "\n".join(output)