2 # GoodFET ARM Client Library
4 # Contributions and bug reports welcome.
7 # * full cycle debugging.. halt to resume
8 # * ensure correct PC handling
9 # * flash manipulation (probably need to get the specific chip for this one)
10 # * set security (chip-specific)
12 import sys, binascii, struct, time
13 from GoodFET import GoodFET
14 from intelhex import IntelHex
30 # ARM7TDMI JTAG commands
39 # Really ARM specific stuff
64 EICE_DBGCTRL = 0 # read 3 bit - Debug Control
65 EICE_DBGCTRL_BITLEN = 3
66 EICE_DBGSTATUS = 1 # read 5 bit - Debug Status
67 EICE_DBGSTATUS_BITLEN = 5
68 EICE_DBGCCR = 4 # read 6 bit - Debug Comms Control Register
69 EICE_DBGCCR_BITLEN = 6
70 EICE_DBGCDR = 5 # r/w 32 bit - Debug Comms Data Register
71 EICE_WP0ADDR = 8 # r/w 32 bit - Watchpoint 0 Address
72 EICE_WP0ADDRMASK = 9 # r/w 32 bit - Watchpoint 0 Addres Mask
73 EICE_WP0DATA = 10 # r/w 32 bit - Watchpoint 0 Data
74 EICE_WP0DATAMASK = 11 # r/w 32 bit - Watchpoint 0 Data Masl
75 EICE_WP0CTRL = 12 # r/w 9 bit - Watchpoint 0 Control Value
76 EICE_WP0CTRLMASK = 13 # r/w 8 bit - Watchpoint 0 Control Mask
77 EICE_WP1ADDR = 16 # r/w 32 bit - Watchpoint 0 Address
78 EICE_WP1ADDRMASK = 17 # r/w 32 bit - Watchpoint 0 Addres Mask
79 EICE_WP1DATA = 18 # r/w 32 bit - Watchpoint 0 Data
80 EICE_WP1DATAMASK = 19 # r/w 32 bit - Watchpoint 0 Data Masl
81 EICE_WP1CTRL = 20 # r/w 9 bit - Watchpoint 0 Control Value
82 EICE_WP1CTRLMASK = 21 # r/w 8 bit - Watchpoint 0 Control Mask
99 0: ("UNKNOWN, MESSED UP PROCESSOR MODE","fsck", "This should Never happen. MCU is in funky state!"),
100 PM_usr: ("User Processor Mode", "usr", "Normal program execution mode"),
101 PM_fiq: ("FIQ Processor Mode", "fiq", "Supports a high-speed data transfer or channel process"),
102 PM_irq: ("IRQ Processor Mode", "irq", "Used for general-purpose interrupt handling"),
103 PM_svc: ("Supervisor Processor Mode", "svc", "A protected mode for the operating system"),
104 PM_abt: ("Abort Processor Mode", "abt", "Implements virtual memory and/or memory protection"),
105 PM_und: ("Undefined Processor Mode", "und", "Supports software emulation of hardware coprocessor"),
106 PM_sys: ("System Processor Mode", "sys", "Runs privileged operating system tasks (ARMv4 and above)"),
110 None, None, None, None, None, "Thumb", "nFIQ_int", "nIRQ_int",
111 "nImprDataAbort_int", "BIGendian", None, None, None, None, None, None,
112 "GE_0", "GE_1", "GE_2", "GE_3", None, None, None, None,
113 "Jazelle", None, None, "Q (DSP-overflow)", "oVerflow", "Carry", "Zero", "Neg",
116 ARM_INSTR_NOP = 0xe1a00000L
117 ARM_INSTR_BX_R0 = 0xe12fff10L
118 ARM_INSTR_STR_Rx_r14 = 0xe58f0000L # from atmel docs
119 ARM_READ_REG = ARM_INSTR_STR_Rx_r14
120 ARM_INSTR_LDR_Rx_r14 = 0xe59f0000L # from atmel docs
121 ARM_WRITE_REG = ARM_INSTR_LDR_Rx_r14
122 ARM_INSTR_LDR_R1_r0_4 = 0xe4901004L
123 ARM_READ_MEM = ARM_INSTR_LDR_R1_r0_4
124 ARM_INSTR_STR_R1_r0_4 = 0xe4801004L
125 ARM_WRITE_MEM = ARM_INSTR_STR_R1_r0_4
126 ARM_INSTR_STRB_R1_r0_1 = 0xe4c01001L
127 ARM_WRITE_MEM_BYTE = ARM_INSTR_STRB_R1_r0_1
128 ARM_INSTR_MRS_R0_CPSR = 0xe10f0000L
129 ARM_INSTR_MSR_cpsr_cxsf_R0 =0xe12ff000L
130 ARM_INSTR_STMIA_R14_r0_rx = 0xE88e0000L # add up to 65k to indicate which registers...
131 ARM_INSTR_LDMIA_R14_r0_rx = 0xE89e0000L # add up to 65k to indicate which registers...
132 ARM_STORE_MULTIPLE = ARM_INSTR_STMIA_R14_r0_rx
133 ARM_INSTR_SKANKREGS = 0xE88F7fffL
134 ARM_INSTR_CLOBBEREGS = 0xE89F7fffL
136 ARM_INSTR_B_IMM = 0xea000000L
137 ARM_INSTR_B_PC = 0xea000000L
138 ARM_INSTR_BX_PC = 0xe1200010L # need to set r0 to the desired address
139 THUMB_INSTR_LDR_R0_r0 = 0x68006800L
140 THUMB_WRITE_REG = THUMB_INSTR_LDR_R0_r0
141 THUMB_INSTR_STR_R0_r0 = 0x60006000L
142 THUMB_READ_REG = THUMB_INSTR_STR_R0_r0
143 THUMB_INSTR_MOV_R0_PC = 0x46b846b8L
144 THUMB_INSTR_MOV_PC_R0 = 0x46474647L
145 THUMB_INSTR_BX_PC = 0x47784778L
146 THUMB_INSTR_NOP = 0x1c001c00L
147 THUMB_INSTR_B_IMM = 0xe000e000L
181 LDM_BITMASKS = [(1<<x)-1 for x in xrange(16)]
182 #### TOTALLY BROKEN, NEED VALIDATION AND TESTING
189 print >>sys.stderr,(strng)
190 def PSRdecode(psrval):
191 output = [ "(%s mode)"%proc_modes[psrval&0x1f][1] ]
192 for x in xrange(5,32):
194 output.append(PSR_bits[x])
195 return " ".join(output)
197 fmt = [None, "B", "<H", None, "<L", None, None, None, "<Q"]
199 s = struct.pack(fmt[byts], val)
200 return [ord(b) for b in s ]
202 class GoodFETARM(GoodFET):
203 """A GoodFET variant for use with ARM7TDMI microprocessor."""
205 GoodFET.__init__(self)
206 self.storedPC = 0xffffffff
207 self.current_dbgstate = 0xffffffff
208 self.flags = 0xffffffff
209 self.nothing = 0xffffffff
212 if (self.ARMget_dbgstate()&9) == 9:
215 sys.excepthook(*sys.exc_info())
217 """Move the FET into the JTAG ARM application."""
218 #print "Initializing ARM."
219 self.writecmd(0x13,SETUP,0,self.data)
221 return self.ARMgetPC()
222 def flash(self,file):
223 """Flash an intel hex file to code memory."""
224 print "Flash not implemented.";
225 def dump(self,file,start=0,stop=0xffff):
226 """Dump an intel hex file from code memory."""
227 print "Dump not implemented.";
228 def ARMshift_IR(self, IR, noretidle=0):
229 self.writecmd(0x13,IR_SHIFT,2, [IR, LSB|noretidle])
231 def ARMshift_DR(self, data, bits, flags):
232 self.writecmd(0x13,DR_SHIFT,14,[bits&0xff, flags&0xff, 0, 0, data&0xff,(data>>8)&0xff,(data>>16)&0xff,(data>>24)&0xff, (data>>32)&0xff,(data>>40)&0xff,(data>>48)&0xff,(data>>56)&0xff,(data>>64)&0xff,(data>>72)&0xff])
234 def ARMshift_DR_more(self, data, bits, flags):
235 self.writecmd(0x13,DR_SHIFT_MORE,14,[bits&0xff, flags&0xff, 0, 0, data&0xff,(data>>8)&0xff,(data>>16)&0xff,(data>>24)&0xff, (data>>32)&0xff,(data>>40)&0xff,(data>>48)&0xff,(data>>56)&0xff,(data>>64)&0xff,(data>>72)&0xff])
237 def ARMwaitDBG(self, timeout=0xff):
238 self.current_dbgstate = self.ARMget_dbgstate()
239 while ( not ((self.current_dbgstate & 9L) == 9)):
241 self.current_dbgstate = self.ARMget_dbgstate()
244 """Get an ARM's ID."""
245 self.ARMshift_IR(IR_IDCODE,0)
246 self.ARMshift_DR(0,32,LSB)
247 retval = struct.unpack("<L", "".join(self.data[0:4]))[0]
249 def ARMidentstr(self):
250 ident=self.ARMident()
252 partno = (ident >> 12) & 0xffff
253 mfgid = (ident >> 1) & 0x7ff
254 return "Chip IDCODE: 0x%x\n\tver: %x\n\tpartno: %x\n\tmfgid: %x\n" % (ident, ver, partno, mfgid);
255 def ARMeice_write(self, reg, val):
258 retval = self.writecmd(0x13, EICE_WRITE, 5, data)
260 def ARMeice_read(self, reg):
261 self.writecmd(0x13, EICE_READ, 1, [reg])
262 retval, = struct.unpack("<L",self.data)
264 def ARMget_dbgstate(self):
265 """Read the config register of an ARM."""
266 self.ARMeice_read(EICE_DBGSTATUS)
267 self.current_dbgstate = struct.unpack("<L", self.data[:4])[0]
268 return self.current_dbgstate
269 status = ARMget_dbgstate
271 """Check the status as a string."""
277 str="%s %s" %(self.ARMstatusbits[i],str)
280 def ARMget_dbgctrl(self):
281 """Read the config register of an ARM."""
282 self.ARMeice_read(EICE_DBGCTRL)
283 retval = struct.unpack("<L", self.data[:4])[0]
285 def ARMset_dbgctrl(self,config):
286 """Write the config register of an ARM."""
287 self.ARMeice_write(EICE_DBGCTRL, config&7)
289 """Get an ARM's PC. Note: real PC gets all wonky in debug mode, this is the "saved" PC"""
291 def ARMsetPC(self, val):
292 """Set an ARM's PC. Note: real PC gets all wonky in debug mode, this changes the "saved" PC which is used when exiting debug mode"""
294 def ARMget_register(self, reg):
295 """Get an ARM's Register"""
296 self.writecmd(0x13,GET_REGISTER,1,[reg&0xf])
297 retval = struct.unpack("<L", "".join(self.data[0:4]))[0]
299 def ARMset_register(self, reg, val):
300 """Get an ARM's Register"""
301 self.writecmd(0x13,SET_REGISTER,8,[val&0xff, (val>>8)&0xff, (val>>16)&0xff, val>>24, reg,0,0,0])
302 retval = struct.unpack("<L", "".join(self.data[0:4]))[0]
304 def ARMget_registers(self):
305 """Get ARM Registers"""
306 regs = [ self.ARMget_register(x) for x in range(15) ]
307 regs.append(self.ARMgetPC()) # make sure we snag the "static" version of PC
309 def ARMset_registers(self, regs, mask):
310 """Set ARM Registers"""
313 self.ARMset_register(x,regs.pop(0))
314 if (1<<15) & mask: # make sure we set the "static" version of PC or changes will be lost
315 self.ARMsetPC(regs.pop(0))
316 def ARMdebuginstr(self,instr,bkpt):
317 if type (instr) == int or type(instr) == long:
318 instr = struct.pack("<L", instr)
319 instr = [int("0x%x"%ord(x),16) for x in instr]
321 self.writecmd(0x13,DEBUG_INSTR,len(instr),instr)
323 def ARM_nop(self, bkpt=0):
324 if self.status() & DBG_TBIT:
325 return self.ARMdebuginstr(THUMB_INSTR_NOP, bkpt)
326 return self.ARMdebuginstr(ARM_INSTR_NOP, bkpt)
327 def ARMrestart(self):
328 self.ARMshift_IR(IR_RESTART)
329 def ARMset_watchpoint0(self, addr, addrmask, data, datamask, ctrl, ctrlmask):
330 self.ARMeice_write(EICE_WP0ADDR, addr); # write 0 in watchpoint 0 address
331 self.ARMeice_write(EICE_WP0ADDRMASK, addrmask); # write 0xffffffff in watchpoint 0 address mask
332 self.ARMeice_write(EICE_WP0DATA, data); # write 0 in watchpoint 0 data
333 self.ARMeice_write(EICE_WP0DATAMASK, datamask); # write 0xffffffff in watchpoint 0 data mask
334 self.ARMeice_write(EICE_WP0CTRL, ctrl); # write 0x00000100 in watchpoint 0 control value register (enables watchpoint)
335 self.ARMeice_write(EICE_WP0CTRLMASK, ctrlmask); # write 0xfffffff7 in watchpoint 0 control mask - only detect the fetch instruction
337 def ARMset_watchpoint1(self, addr, addrmask, data, datamask, ctrl, ctrlmask):
338 self.ARMeice_write(EICE_WP1ADDR, addr); # write 0 in watchpoint 1 address
339 self.ARMeice_write(EICE_WP1ADDRMASK, addrmask); # write 0xffffffff in watchpoint 1 address mask
340 self.ARMeice_write(EICE_WP1DATA, data); # write 0 in watchpoint 1 data
341 self.ARMeice_write(EICE_WP1DATAMASK, datamask); # write 0xffffffff in watchpoint 1 data mask
342 self.ARMeice_write(EICE_WP1CTRL, ctrl); # write 0x00000100 in watchpoint 1 control value register (enables watchpoint)
343 self.ARMeice_write(EICE_WP1CTRLMASK, ctrlmask); # write 0xfffffff7 in watchpoint 1 control mask - only detect the fetch instruction
345 def THUMBgetPC(self):
346 THUMB_INSTR_STR_R0_r0 = 0x60006000L
347 THUMB_INSTR_MOV_R0_PC = 0x46b846b8L
348 THUMB_INSTR_BX_PC = 0x47784778L
349 THUMB_INSTR_NOP = 0x1c001c00L
351 r0 = self.ARMget_register(0)
352 self.ARMdebuginstr(THUMB_INSTR_MOV_R0_PC, 0)
353 retval = self.ARMget_register(0)
354 self.ARMset_register(0,r0)
356 def ARMcapture_system_state(self, pcoffset):
357 if self.ARMget_dbgstate() & DBG_TBIT:
361 self.storedPC = self.ARMget_register(15) + pcoffset
362 self.last_dbg_state = self.ARMget_dbgstate()
363 def ARMhaltcpu(self):
365 if not(self.ARMget_dbgstate()&1):
366 self.ARMset_dbgctrl(2)
367 if (self.ARMwaitDBG() == 0):
368 raise Exception("Timeout waiting to enter DEBUG mode on HALT")
369 self.ARMset_dbgctrl(0)
370 self.ARMcapture_system_state(PCOFF_DBGRQ)
371 if self.last_dbg_state&0x10:
372 self.storedPC = self.THUMBgetPC()
374 self.storedPC = self.ARMget_register(15)
375 self.storedPC, self.flags, self.nothing = self.ARMchain0(0)
376 if self.ARMget_dbgstate() & DBG_TBIT:
378 if self.storedPC ^ 4:
379 self.ARMset_register(15,self.storedPC&0xfffffffc)
380 print "CPSR: (%s) %s"%(self.ARMget_regCPSRstr())
382 def ARMreleasecpu(self):
383 """Resume the CPU."""
384 # restore registers FIXME: DO THIS
385 if self.ARMget_dbgstate()&1 == 0:
387 currentPC, self.currentflags, nothing = self.ARMchain0(self.storedPC,self.flags)
388 if not(self.flags & F_TBIT): # need to be in arm mode
389 if self.currentflags & F_TBIT: # currently in thumb mode
391 # branch to the right address
392 self.ARMset_register(15, self.storedPC)
393 print hex(self.storedPC)
394 print hex(self.ARMget_register(15))
395 print hex(self.ARMchain0(self.storedPC,self.flags)[0])
398 self.ARMdebuginstr(ARM_INSTR_B_IMM | 0xfffff0,0)
402 elif self.flags & F_TBIT: # need to be in thumb mode
403 if not (self.currentflags & F_TBIT): # currently in arm mode
404 self.ARMsetModeThumb()
405 r0=self.ARMget_register(0)
406 self.ARMset_register(0, self.storedPC)
407 self.ARMdebuginstr(THUMB_INSTR_MOV_PC_R0,0)
410 print hex(self.storedPC)
411 print hex(self.ARMget_register(15))
412 print hex(self.ARMchain0(self.storedPC,self.flags)[0])
413 self.ARMdebuginstr(THUMB_INSTR_B_IMM | (0x7fc07fc),0)
418 resume = ARMreleasecpu
420 self.writecmd(0x13, RESETTAP, 0,[])
421 def ARMsetModeARM(self):
423 if ((self.current_dbgstate & DBG_TBIT)):
424 debugstr("=== Switching to ARM mode ===")
426 self.ARMdebuginstr(THUMB_INSTR_BX_PC,0)
430 self.current_dbgstate = self.ARMget_dbgstate();
431 return self.current_dbgstate
432 def ARMsetModeThumb(self): # needs serious work and truing
434 debugstr("=== Switching to THUMB mode ===")
435 if ( not (self.current_dbgstate & DBG_TBIT)):
437 r0 = self.ARMget_register(0)
438 self.ARMset_register(0, self.storedPC)
440 self.ARMdebuginstr(ARM_INSTR_BX_R0,0)
444 self.ARMset_register(0,r0)
445 self.current_dbgstate = self.ARMget_dbgstate();
446 return self.current_dbgstate
447 def ARMget_regCPSRstr(self):
448 psr = self.ARMget_regCPSR()
449 return hex(psr), PSRdecode(psr)
450 def ARMget_regCPSR(self):
451 """Get an ARM's Register"""
452 r0 = self.ARMget_register(0)
453 self.ARM_nop( 0) # push nop into pipeline - clean out the pipeline...
454 self.ARMdebuginstr(ARM_INSTR_MRS_R0_CPSR, 0) # push MRS_R0, CPSR into pipeline - fetch
455 self.ARM_nop( 0) # push nop into pipeline - decoded
456 self.ARM_nop( 0) # push nop into pipeline - execute
457 retval = self.ARMget_register(0)
458 self.ARMset_register(0, r0)
460 def ARMset_regCPSR(self, val):
461 """Get an ARM's Register"""
462 r0 = self.ARMget_register(0)
463 self.ARMset_register(0, val)
464 self.ARM_nop( 0) # push nop into pipeline - clean out the pipeline...
465 self.ARMdebuginstr(ARM_INSTR_MSR_cpsr_cxsf_R0, 0) # push MSR cpsr_cxsf, R0 into pipeline - fetch
466 self.ARM_nop( 0) # push nop into pipeline - decoded
467 self.ARM_nop( 0) # push nop into pipeline - execute
468 self.ARMset_register(0, r0)
470 def ARMreadMem(self, adr, wrdcount=1):
472 r0 = self.ARMget_register(0); # store R0 and R1
473 r1 = self.ARMget_register(1);
474 #print >>sys.stderr,("CPSR:\t%x"%self.ARMget_regCPSR())
475 self.ARMset_register(0, adr); # write address into R0
476 self.ARMset_register(1, 0xdeadbeef)
477 for word in range(adr, adr+(wrdcount*4), 4):
478 #sys.stdin.readline()
481 self.ARMdebuginstr(ARM_READ_MEM, 0); # push LDR R1, [R0], #4 into instruction pipeline (autoincrements for consecutive reads)
485 print hex(self.ARMget_register(1))
487 # FIXME: this may end up changing te current debug-state. should we compare to current_dbgstate?
488 #print repr(self.data[4])
489 if (len(self.data)>4 and self.data[4] == '\x00'):
490 print >>sys.stderr,("FAILED TO READ MEMORY/RE-ENTER DEBUG MODE")
491 raise Exception("FAILED TO READ MEMORY/RE-ENTER DEBUG MODE")
494 retval.append( self.ARMget_register(1) ) # read memory value from R1 register
495 #print >>sys.stderr,("CPSR: %x\t\tR0: %x\t\tR1: %x"%(self.ARMget_regCPSR(),self.ARMget_register(0),self.ARMget_register(1)))
496 self.ARMset_register(1, r1); # restore R0 and R1
497 self.ARMset_register(0, r0);
499 def ARMreadChunk(self, adr, wordcount):
500 """ Only works in ARM mode currently
501 WARNING: Addresses must be word-aligned!
503 regs = self.ARMget_registers()
504 self.ARMset_registers([0xdeadbeef for x in xrange(14)], 0xe)
507 while (wordcount > 0):
508 if (wordcount%64 == 0): sys.stderr.write(".")
509 count = (wordcount, 0xe)[wordcount>0xd]
510 bitmask = LDM_BITMASKS[count]
511 self.ARMset_register(14,adr)
513 self.ARMdebuginstr(ARM_INSTR_LDMIA_R14_r0_rx | bitmask ,0)
514 #FIXME: do we need the extra nop here?
517 output.extend([self.ARMget_register(x) for x in xrange(count)])
521 # FIXME: handle the rest of the wordcount here.
522 self.ARMset_registers(regs,0xe)
524 def ARMreadStream(self, adr, bytecount):
525 data = [struct.unpack("<L", x) for x in self.ARMreadChunk(adr, (bytecount-1/4)+1)]
526 return "".join(data)[:bytecount]
528 def ARMwriteChunk(self, adr, wordarray):
529 """ Only works in ARM mode currently
530 WARNING: Addresses must be word-aligned!
532 regs = self.ARMget_registers()
533 wordcount = len(wordarray)
534 while (wordcount > 0):
535 if (wordcount%64 == 0): sys.stderr.write(".")
536 count = (wordcount, 0xe)[wordcount>0xd]
537 bitmask = LDM_BITMASKS[count]
538 self.ARMset_register(14,adr)
539 #print len(wordarray),bin(bitmask)
540 self.ARMset_registers(wordarray[:count],bitmask)
542 self.ARMdebuginstr(ARM_INSTR_STMIA_R14_r0_rx | bitmask ,0)
543 #FIXME: do we need the extra nop here?
546 wordarray = wordarray[count:]
550 # FIXME: handle the rest of the wordcount here.
551 def ARMwriteMem(self, adr, wordarray, instr=ARM_WRITE_MEM):
552 r0 = self.ARMget_register(0); # store R0 and R1
553 r1 = self.ARMget_register(1);
554 #print >>sys.stderr,("CPSR:\t%x"%self.ARMget_regCPSR())
555 for widx in xrange(len(wordarray)):
556 address = adr + (widx*4)
557 word = wordarray[widx]
558 self.ARMset_register(0, address); # write address into R0
559 self.ARMset_register(1, word); # write address into R0
562 self.ARMdebuginstr(instr, 0); # push STR R1, [R0], #4 into instruction pipeline (autoincrements for consecutive writes)
566 print >>sys.stderr,hex(self.ARMget_register(1))
567 self.ARMset_register(1, r1); # restore R0 and R1
568 self.ARMset_register(0, r0);
569 def writeMemByte(self, adr, byte):
570 self.ARMwriteMem(adr, byte, ARM_WRITE_MEM_BYTE)
576 0x04 : "Interrupts Enabled (or not?)",
581 0x04 : "disable interrupts",
582 0x02 : "force dbgrq",
583 0x01 : "force dbgack"
585 def ARMresettarget(self, delay=10):
586 return self.writecmd(0x13,RESETTARGET,2, [ delay&0xff, (delay>>8)&0xff ] )
587 def ARMchain0(self, address, bits=0x819684c054, data=0):
588 bulk = chop(address,4)
589 bulk.extend(chop(bits,8))
590 bulk.extend(chop(data,4))
591 print >>sys.stderr,(repr(bulk))
592 self.writecmd(0x13,CHAIN0,16,bulk)
593 d1,b1,a1 = struct.unpack("<LQL",self.data)
596 """Start debugging."""
597 self.writecmd(0x13,START,0,self.data)
598 print >>sys.stderr,"Identifying Target:"
599 ident=self.ARMidentstr()
600 print >>sys.stderr,ident
601 print >>sys.stderr,"Debug Status:\t%s\n" % self.statusstr()
604 """Stop debugging."""
605 self.writecmd(0x13,STOP,0,self.data)
606 #def ARMstep_instr(self):
607 # """Step one instruction."""
608 # self.writecmd(0x13,STEP_INSTR,0,self.data)
609 #def ARMflashpage(self,adr):
610 # """Flash 2kB a page of flash from 0xF000 in XDATA"""
615 # print "Flashing buffer to 0x%06x" % adr
616 # self.writecmd(0x13,MASS_FLASH_PAGE,4,data)