2 \author Travis Goodspeed
3 \brief Chipcon 8051 debugging.
7 //This is like SPI, except that you read or write, not both.
9 /* N.B. The READ verb performs a write of all (any) supplied data,
10 then reads a single byte reply from the target. The WRITE verb
22 //! Handles a chipcon command.
23 void cc_handle_fn( uint8_t const app,
27 // define the jtag app's app_t
28 app_t const chipcon_app = {
40 "\tThe CHIPCON app adds support for debugging the chipcon\n"
44 /* Concerning clock rates, the maximimum clock rates are defined on
45 page 4 of the spec. They vary, but are roughly 30MHz. Raising
46 this clock rate might allow for clock glitching, but the GoodFET
47 isn't sufficient fast for that. Perhaps a 200MHz ARM or an FPGA in
52 //MISO and MOSI are the same pin, direction changes.
59 //This could be more accurate.
60 //Does it ever need to be?
63 //#define CCDELAY(x) delay(x)
66 #define SETMOSI SPIOUT|=MOSI
67 #define CLRMOSI SPIOUT&=~MOSI
68 #define SETCLK SPIOUT|=SCK
69 #define CLRCLK SPIOUT&=~SCK
70 #define READMISO (SPIIN&MISO?1:0)
72 #define CCWRITE SPIDIR|=MOSI
73 #define CCREAD SPIDIR&=~MISO
75 //! Set up the pins for CC mode. Does not init debugger.
83 /* 33 cycle critical region
84 0000000e <ccdebuginit>:
85 e: f2 d0 0d 00 bis.b #13, &0x0031 ;5 cycles
87 14: f2 c2 31 00 bic.b #8, &0x0031 ;4 cycles
88 18: d2 c3 31 00 bic.b #1, &0x0031 ;4
89 1c: f2 e2 31 00 xor.b #8, &0x0031 ;4
90 20: f2 e2 31 00 xor.b #8, &0x0031 ;4
91 24: f2 e2 31 00 xor.b #8, &0x0031 ;4
92 28: f2 e2 31 00 xor.b #8, &0x0031 ;4
93 2c: d2 d3 31 00 bis.b #1, &0x0031 ;4
98 //! Initialize the debugger
100 //Port output BUT NOT DIRECTION is set at start.
101 SPIOUT|=MOSI+SCK+RST;
103 delay(30); //So the beginning is ready for glitching.
105 //Two positive debug clock pulses while !RST is low.
106 //Take RST low, pulse twice, then high.
120 SPIOUT^=SCK; //Unnecessary.
128 //! Read and write a CC bit.
129 unsigned char cctrans8(unsigned char byte){
131 //This function came from the SPI Wikipedia article.
134 for (bit = 0; bit < 8; bit++) {
135 /* write MOSI on trailing edge of previous clock */
142 /* half a clock cycle before leading/rising edge */
146 /* half a clock cycle before trailing/falling edge */
149 /* read MISO on trailing edge */
157 //! Send a command from txbytes.
158 void cccmd(unsigned char len){
162 cctrans8(cmddata[i]);
165 //! Fetch a reply, usually 1 byte.
166 void ccread(unsigned char len){
170 cmddata[i]=cctrans8(0);
173 //! Handles a chipcon command.
174 void cc_handle_fn( uint8_t const app,
178 //Always init. Might help with buggy lines.
182 int blocklen, blockadr;
185 //CC_PEEK and CC_POKE will come later.
187 cmddata[0]=cc_peekirambyte(cmddata[0]);
191 cmddata[0]=cc_pokeirambyte(cmddata[0],cmddata[1]);
194 case READ: //Write a command and return 1-byte reply.
200 case WRITE: //Write a command with no reply.
204 case START://enter debugger
208 case STOP://exit debugger
209 //Take RST low, then high.
222 case CC_MASS_ERASE_FLASH:
227 cc_wr_config(cmddata[0]);
240 //no break, return status
245 case CC_SET_HW_BRKPNT:
246 cc_set_hw_brkpnt(cmddataword[0]);
265 case CC_STEP_REPLACE:
266 txdata(app,NOK,0);//Don't add this; it's non-standard.
269 cmddataword[0]=cc_get_chip_id();
275 case CC_READ_CODE_MEMORY:
276 cmddata[0]=cc_peekcodebyte(cmddataword[0]);
279 case CC_READ_XDATA_MEMORY:
283 blocklen=cmddataword[1];
284 blockadr=cmddataword[0];
286 //Return that many bytes.
287 for(i=0;i<blocklen;i++)
288 cmddata[i]=cc_peekdatabyte(blockadr+i);
289 txdata(app,verb,blocklen);
292 case CC_WRITE_XDATA_MEMORY:
293 cmddata[0]=cc_pokedatabyte(cmddataword[0], cmddata[2]);
297 cc_set_pc(cmddatalong[0]);
300 case CC_WRITE_FLASH_PAGE:
301 cc_write_flash_page(cmddatalong[0]);
304 case CC_WIPEFLASHBUFFER:
305 for(i=0xf000;i<0xf800;i++)
306 cc_pokedatabyte(i,0xFF);
311 case CC_PROGRAM_FLASH:
313 debugstr("This Chipcon command is not yet implemented.");
314 txdata(app,NOK,0);//TODO implement me.
319 //! Set the Chipcon's Program Counter
320 void cc_set_pc(u32 adr){
321 cmddata[0]=0x02; //SetPC
322 cmddata[1]=((adr>>8)&0xff); //HIBYTE
323 cmddata[2]=adr&0xff; //LOBYTE
328 //! Erase all of a Chipcon's memory.
329 void cc_chip_erase(){
330 cmddata[0]=CCCMD_CHIP_ERASE; //0x14
334 //! Write the configuration byte.
335 void cc_wr_config(unsigned char config){
336 cmddata[0]=CCCMD_WR_CONFIG; //0x1D
346 //debugstr("Locking chip.");
347 cc_wr_config(1);//Select Info Flash
348 if(!(cc_rd_config()&1))
349 debugstr("Config forgotten!");
353 cc_pokedatabyte(0xf000+i,0);
354 cc_write_flash_page(0);
355 if(cc_peekcodebyte(0))
356 debugstr("Failed to clear info flash byte.");
360 debugstr("Stuck in info flash mode!");
363 //! Read the configuration byte.
364 unsigned char cc_rd_config(){
365 cmddata[0]=CCCMD_RD_CONFIG; //0x24
372 //! Read the status register
373 unsigned char cc_read_status(){
374 cmddata[0]=CCCMD_READ_STATUS; //0x3f
380 //! Read the CHIP ID bytes.
381 unsigned short cc_get_chip_id(){
382 cmddata[0]=CCCMD_GET_CHIP_ID; //0x68
387 //Find the flash word size.
393 //debugstr("2 bytes/flash word");
394 flash_word_size=0x02;
397 //debugstr("Warning: Guessing flash word size.");
402 //debugstr("4 bytes/flash word");
403 flash_word_size=0x04;
408 return cmddataword[0];
411 //! Populates flash buffer in xdata.
412 void cc_write_flash_buffer(u8 *data, u16 len){
413 cc_write_xdata(0xf000, data, len);
415 //! Populates flash buffer in xdata.
416 void cc_write_xdata(u16 adr, u8 *data, u16 len){
418 for(i=0; i<len; i++){
419 cc_pokedatabyte(adr+i,
425 //32-bit words, 2KB pages
426 //0x20 0x00 for CC2430, CC1110
427 #define HIBYTE_WORDS_PER_FLASH_PAGE 0x02
428 #define LOBYTE_WORDS_PER_FLASH_PAGE 0x00
430 /** Ugh, this varies by chip.
434 //#define FLASHPAGE_SIZE 0x400
435 #define MAXFLASHPAGE_SIZE 0x800
436 #define MINFLASHPAGE_SIZE 0x400
439 //32 bit words on CC2430
440 //16 bit words on CC1110
441 //#define FLASH_WORD_SIZE 0x2
442 u8 flash_word_size = 0; //0x02;
445 /* Flash Write Timing
452 32 | 0x2A (Modula.si)
456 const u8 flash_routine[] = {
460 0x00,//#imm=((address >> 8) / FLASH_WORD_SIZE) & 0x7E,
462 //0x75, 0xAB, 0x23, //Set FWT per clock
463 0x75, 0xAC, 0x00, // MOV FADDRL, #00;
465 0x75, 0xAE, 0x01, // MOV FLC, #01H; // ERASE
466 // ; Wait for flash erase to complete
467 0xE5, 0xAE, // eraseWaitLoop: MOV A, FLC;
468 0x20, 0xE7, 0xFB, // JB ACC_BUSY, eraseWaitLoop;
470 /* End erase page. */
471 // ; Initialize the data pointer
472 0x90, 0xF0, 0x00, // MOV DPTR, #0F000H;
474 0x7F, HIBYTE_WORDS_PER_FLASH_PAGE, // MOV R7, #imm;
475 0x7E, LOBYTE_WORDS_PER_FLASH_PAGE, // MOV R6, #imm;
476 0x75, 0xAE, 0x02, // MOV FLC, #02H; // WRITE
479 0x7D, 0xde /*FLASH_WORD_SIZE*/, // writeLoop: MOV R5, #imm;
480 0xE0, // writeWordLoop: MOVX A, @DPTR;
482 0xF5, 0xAF, // MOV FWDATA, A;
483 0xDD, 0xFA, // DJNZ R5, writeWordLoop;
484 // ; Wait for completion
485 0xE5, 0xAE, // writeWaitLoop: MOV A, FLC;
486 0x20, 0xE6, 0xFB, // JB ACC_SWBSY, writeWaitLoop;
487 0xDE, 0xF1, // DJNZ R6, writeLoop;
488 0xDF, 0xEF, // DJNZ R7, writeLoop;
489 // ; Done, fake a breakpoint
494 //! Copies flash buffer to flash.
495 void cc_write_flash_page(u32 adr){
496 //Assumes that page has already been written to XDATA 0xF000
497 //debugstr("Flashing 2kb at 0xF000 to given adr.");
499 if(adr&(MINFLASHPAGE_SIZE-1)){
500 debugstr("Flash page address is not on a page boundary. Aborting.");
504 if(flash_word_size!=2 && flash_word_size!=4){
505 debugstr("Flash word size is wrong, aborting write to");
511 //WRITE_XDATA_MEMORY(IN: 0xF000 + FLASH_PAGE_SIZE, sizeof(routine), routine);
512 cc_write_xdata(0xF000+MAXFLASHPAGE_SIZE,
513 (u8*) flash_routine, sizeof(flash_routine));
514 //Patch routine's third byte with
515 //((address >> 8) / FLASH_WORD_SIZE) & 0x7E
516 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+2,
517 ((adr>>8)/flash_word_size)&0x7E);
518 //Patch routine to define FLASH_WORD_SIZE
519 if(flash_routine[25]!=0xde)
520 debugstr("Ugly patching code failing in chipcon.c");
521 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+25,
524 //debugstr("Wrote flash routine.");
526 //MOV MEMCTR, (bank * 16) + 1;
531 //debugstr("Loaded bank info.");
533 cc_set_pc(0xf000+MAXFLASHPAGE_SIZE);//execute code fragment
536 //debugstr("Executing.");
539 while(!(cc_read_status()&CC_STATUS_CPUHALTED)){
540 PLEDOUT^=PLEDPIN;//blink LED while flashing
544 //debugstr("Done flashing.");
546 PLEDOUT&=~PLEDPIN;//clear LED
550 unsigned short cc_get_pc(){
551 cmddata[0]=CCCMD_GET_PC; //0x28
556 return cmddataword[0];
559 //! Set a hardware breakpoint.
560 void cc_set_hw_brkpnt(unsigned short adr){
561 debugstr("FIXME: This certainly won't work.");
571 cmddata[0]=CCCMD_HALT; //0x44
578 cmddata[0]=CCCMD_RESUME; //0x4C
585 //! Step an instruction
586 void cc_step_instr(){
587 cmddata[0]=CCCMD_STEP_INSTR; //0x5C
593 //! Debug an instruction.
594 void cc_debug_instr(unsigned char len){
595 //Bottom two bits of command indicate length.
596 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3); //0x54+len
598 cctrans8(cmd); //Second command code
599 cccmd(len&0x3); //Command itself.
604 //! Debug an instruction, for local use.
605 unsigned char cc_debug(unsigned char len,
609 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3);//0x54+len
619 return cctrans8(0x00);
622 //! Fetch a byte of code memory.
623 unsigned char cc_peekcodebyte(unsigned long adr){
624 /** See page 9 of SWRA124 */
625 unsigned char bank=adr>>15,
631 //MOV MEMCTR, (bank*16)+1
632 cc_debug(3, 0x75, 0xC7, (bank<<4) + 1);
634 cc_debug(3, 0x90, hb, lb);
638 cc_debug(2, 0xE4, 0, 0);
640 toret=cc_debug(3, 0x93, 0, 0);
642 //cc_debug(1, 0xA3, 0, 0);
648 //! Set a byte of data memory.
649 unsigned char cc_pokedatabyte(unsigned int adr,
656 cc_debug(3, 0x90, hb, lb);
658 cc_debug(2, 0x74, val, 0);
660 cc_debug(1, 0xF0, 0, 0);
664 DEBUG_INSTR(IN: 0x90, HIBYTE(address), LOBYTE(address), OUT: Discard);
665 for (n = 0; n < count; n++) {
666 DEBUG_INSTR(IN: 0x74, inputArray[n], OUT: Discard);
667 DEBUG_INSTR(IN: 0xF0, OUT: Discard);
668 DEBUG_INSTR(IN: 0xA3, OUT: Discard);
673 //! Fetch a byte of data memory.
674 unsigned char cc_peekdatabyte(unsigned int adr){
680 cc_debug(3, 0x90, hb, lb);
682 //Must be 2, perhaps for clocking?
683 return cc_debug(3, 0xE0, 0, 0);
687 //! Fetch a byte of IRAM.
688 u8 cc_peekirambyte(u8 adr){
690 cc_debug(2, 0xE4, 0, 0);
692 return cc_debug(3, 0xE5, adr, 0);
695 //! Write a byte of IRAM.
696 u8 cc_pokeirambyte(u8 adr, u8 val){
698 cc_debug(2, 0xE4, 0, 0);
700 return cc_debug(3, 0x75, adr, val);
701 //return cc_debug(3, 0x75, val, adr);