1 .globl jtag430_tclk_flashpulses
2 .type jtag430_tclk_flashpulses,@function //for linking
4 //This detects model, chooses appropriate timing.
5 jtag430_tclk_flashpulses:
7 cmp #0x6cf1, r14 ;Is the chip an MSP430F1xx?
8 jz jtag430_tclk_flashpulses_3mhz
9 jmp jtag430_tclk_flashpulses_16mhz
11 // At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz.
12 // At 16MHz, 33 to 62 cycles/loop are allowed.
13 jtag430_tclk_flashpulses_3mhz:
16 bis.b #2, @r14 ;SETTCLK, 3 cycles
18 ;; 1+3+3+1+2=10, within limits
19 bic.b #2, @r14 ;CLRTCLK, 3 cycles
21 jnz pulseloop3 ; 2 cycles
24 jtag430_tclk_flashpulses_16mhz:
27 bis.b #2, @r14 ;SETTCLK, 3 cycles
29 ;; 1+3+3+1+2=10, beneath limits,
31 ;; +3+2=5, repeat 8 times to get 10+40=50, within limits
50 bic.b #2, @r14 ;CLRTCLK, 3 cycles
52 jnz pulseloop16 ; 2 cycles