1 /*! \file jtagarm7tdmi.h
2 \brief JTAG handler functions for the ARM family of processors
8 #define JTAGSTATE_ARM 0 // bit 4 on dbg status reg is low
9 #define JTAGSTATE_THUMB 1
11 unsigned long last_instr = -1;
12 unsigned char last_sysstate = 0;
13 unsigned char last_ir = -1;
14 unsigned char last_scanchain = -1;
15 unsigned char tapstate = 15;
16 unsigned char current_dbgstate = -1;
17 //unsigned char last_halt_debug_state = -1;
18 //unsigned long last_halt_pc = -1;
24 void adiv5_start(void);
26 //! Set a 32-bit ARM register
27 void jtagarm7tdmi_set_register(unsigned long reg, unsigned long val);
28 //! Get a 32-bit ARM register
29 unsigned long jtagarm7tdmi_get_register(unsigned long reg);
32 // DBGRQ - GoodFET Pin 8
36 The instruction register is 4 bits in length.
37 There is no parity bit.
38 The fixed value 0001 is loaded into the instruction register during the CAPTURE-IR
40 The least significant bit of the instruction register is scanned in and scanned out first.
43 //4-bit ARM JTAG INSTRUCTIONS - STANDARD
44 #define ADI_IR_ABORT 0x8
45 #define ADI_IR_RESERVED1 0x9
46 #define ADI_IR_DPACC 0xA
47 #define ADI_IR_APACC 0xB
48 #define ADI_IR_RESERVED2 0xC
49 #define ADI_IR_RESERVED3 0xD
50 #define ADI_IR_IDCODE 0xE
51 #define ADI_IR_BYPASS 0xF
54 //4-bit ARM JTAG INSTRUCTIONS - IMPLEMENTATION-DEFINED
55 #define ADI_IR_EXTEST 0x0
56 #define ADI_IR_SAMPLE 0x1
57 #define ADI_IR_PRELOAD 0x2
58 #define ADI_IR_RESERVED 0x3
59 #define ADI_IR_INTEST 0x4
60 #define ADI_IR_CLAMP 0x5
61 #define ADI_IR_HIGHZ 0x6
62 #define ADI_IR_CLAMPZ 0x7
64 // read 3 bit - Debug Control
65 #define EICE_DBGCTRL 0
66 #define EICE_DBGCTRL_BITLEN 3
67 // read 5 bit - Debug Status
68 #define EICE_DBGSTATUS 1
69 #define EICE_DBGSTATUS_BITLEN 5
70 // read 6 bit - Debug Comms Control Register
72 #define EICE_DBGCCR_BITLEN 6
73 // r/w 32 bit - Debug Comms Data Register
75 // r/w 32 bit - Watchpoint 0 Address
76 #define EICE_WP0ADDR 8
77 // r/w 32 bit - Watchpoint 0 Addres Mask
78 #define EICE_WP0ADDRMASK 9
79 // r/w 32 bit - Watchpoint 0 Data
80 #define EICE_WP0DATA 10
81 // r/w 32 bit - Watchpoint 0 Data Masl
82 #define EICE_WP0DATAMASK 11
83 // r/w 9 bit - Watchpoint 0 Control Value
84 #define EICE_WP0CTRL 12
85 // r/w 8 bit - Watchpoint 0 Control Mask
86 #define EICE_WP0CTRLMASK 13
87 // r/w 32 bit - Watchpoint 0 Address
88 #define EICE_WP1ADDR 16
89 // r/w 32 bit - Watchpoint 0 Addres Mask
90 #define EICE_WP1ADDRMASK 17
91 // r/w 32 bit - Watchpoint 0 Data
92 #define EICE_WP1DATA 18
93 // r/w 32 bit - Watchpoint 0 Data Masl
94 #define EICE_WP1DATAMASK 19
95 // r/w 9 bit - Watchpoint 0 Control Value
96 #define EICE_WP1CTRL 20
97 // r/w 8 bit - Watchpoint 0 Control Mask
98 #define EICE_WP1CTRLMASK 21
102 #define JTAGARM7_GET_REGISTER 0x87
103 #define JTAGARM7_SET_REGISTER 0x88
104 #define JTAGARM7_DEBUG_INSTR 0x89
105 // Really ARM specific stuff
106 #define JTAGARM7_SET_IR 0x90
107 #define JTAGARM7_WAIT_DBG 0x91
108 #define JTAGARM7_SHIFT_DR 0x92
109 #define JTAGARM7_CHAIN0 0x93
110 #define JTAGARM7_SCANCHAIN1 0x94
111 #define JTAGARM7_EICE_READ 0x95
112 #define JTAGARM7_EICE_WRITE 0x96
115 // for deeper understanding, read the instruction cycle timing section of:
116 // http://www.atmel.com/dyn/resources/prod_documents/DDI0029G_7TDMI_R3_trm.pdf
117 #define EXECNOPARM 0xe1a00000L
118 #define ARM_INSTR_NOP 0xe1a00000L
119 #define ARM_INSTR_BX_R0 0xe12fff10L
120 #define ARM_INSTR_STR_Rx_r14 0xe58f0000L // from atmel docs
121 #define ARM_READ_REG ARM_INSTR_STR_Rx_r14
122 #define ARM_INSTR_LDR_Rx_r14 0xe5900000L // NOT from atmel docs (e59e0000L is from atmel docs)
123 #define ARM_WRITE_REG ARM_INSTR_LDR_Rx_r14
124 #define ARM_INSTR_LDR_R1_r0_4 0xe4901004L
125 #define ARM_READ_MEM ARM_INSTR_LDR_R1_r0_4
126 #define ARM_INSTR_STR_R1_r0_4 0xe4801004L
127 #define ARM_WRITE_MEM ARM_INSTR_STR_R1_r0_4
128 #define ARM_INSTR_MRS_R0_CPSR 0xe10f0000L
129 #define ARM_INSTR_MSR_cpsr_cxsf_R0 0xe12ff000L
130 #define ARM_INSTR_STMIA_R14_r0_rx 0xE88E0000L // add up to 65k to indicate which registers...
131 #define ARM_STORE_MULTIPLE ARM_INSTR_STMIA_R14_r0_rx
132 #define ARM_INSTR_SKANKREGS 0xE88F7fffL
133 #define ARM_INSTR_CLOBBEREGS 0xE89F7fffL
135 #define ARM_INSTR_B_IMM 0xea000000L
136 #define ARM_INSTR_BX_PC 0xe12fff10L // need to set r0 to the desired address
137 #define THUMB_INSTR_LDR_R0_r0 0x68006800L
138 #define THUMB_WRITE_REG THUMB_INSTR_LDR_R0_r0
139 #define THUMB_INSTR_STR_R0_r0 0x60006000L
140 #define THUMB_READ_REG THUMB_INSTR_STR_R0_r0
141 #define THUMB_INSTR_MOV_R0_PC 0x46b846b8L
142 #define THUMB_INSTR_MOV_PC_R0 0x46474647L
143 #define THUMB_INSTR_MOV_HiLo 0x46404640L
144 #define THUMB_INSTR_MOV_LoHi 0x46804680L
145 #define THUMB_INSTR_BX_PC 0x47784778L
146 #define THUMB_INSTR_NOP 0x1c001c00L
147 #define THUMB_SWAP_HiLo 0
148 #define THUMB_SWAP_LoHi 1
149 #define ARM_REG_PC 15
151 #define JTAG_ARM_DBG_DBGACK 1
152 #define JTAG_ARM_DBG_DBGRQ 2
153 #define JTAG_ARM_DBG_IFEN 4
154 #define JTAG_ARM_DBG_cgenL 8
155 #define JTAG_ARM_DBG_TBIT 16