1 /*! \file jtagarm7tdmi.h
2 \brief JTAG handler functions for the ARM7TDMI family of processors
12 #define JTAGSTATE_ARM 0 // bit 4 on dbg status reg is low
13 #define JTAGSTATE_THUMB 1
22 #define Capture_DR 0x6
28 #define RunTest_Idle 0xc
30 #define Capture_IR 0xe
31 #define Test_Reset 0xf
36 void jtagarm7tdmi_start(void);
38 //! Set a 32-bit ARM register
39 void jtagarm7tdmi_set_register(unsigned long reg, unsigned long val);
40 //! Get a 32-bit ARM register
41 unsigned long jtagarm7tdmi_get_register(unsigned long reg);
43 // ARM7TDMI-specific pins
44 // DBGRQ - GoodFET Pin 8
48 The instruction register is 4 bits in length.
49 There is no parity bit.
50 The fixed value 0001 is loaded into the instruction register during the CAPTURE-IR
52 The least significant bit of the instruction register is scanned in and scanned out first.
55 //4-bit ARM7TDMI JTAG commands, bit-swapped
56 #define ARM7TDMI_IR_EXTEST 0x0
57 #define ARM7TDMI_IR_SCAN_N 0x2
58 #define ARM7TDMI_IR_SAMPLE 0x3
59 #define ARM7TDMI_IR_RESTART 0x4
60 #define ARM7TDMI_IR_CLAMP 0x5
61 #define ARM7TDMI_IR_HIGHZ 0x7
62 #define ARM7TDMI_IR_CLAMPZ 0x9
63 #define ARM7TDMI_IR_INTEST 0xC
64 #define ARM7TDMI_IR_IDCODE 0xE
65 #define ARM7TDMI_IR_BYPASS 0xF
67 // read 3 bit - Debug Control
68 #define EICE_DBGCTRL 0
69 #define EICE_DBGCTRL_BITLEN 3
70 // read 5 bit - Debug Status
71 #define EICE_DBGSTATUS 1
72 #define EICE_DBGSTATUS_BITLEN 5
73 // read 6 bit - Debug Comms Control Register
75 #define EICE_DBGCCR_BITLEN 6
76 // r/w 32 bit - Debug Comms Data Register
78 // r/w 32 bit - Watchpoint 0 Address
79 #define EICE_WP0ADDR 8
80 // r/w 32 bit - Watchpoint 0 Addres Mask
81 #define EICE_WP0ADDRMASK 9
82 // r/w 32 bit - Watchpoint 0 Data
83 #define EICE_WP0DATA 10
84 // r/w 32 bit - Watchpoint 0 Data Masl
85 #define EICE_WP0DATAMASK 11
86 // r/w 9 bit - Watchpoint 0 Control Value
87 #define EICE_WP0CTRL 12
88 // r/w 8 bit - Watchpoint 0 Control Mask
89 #define EICE_WP0CTRLMASK 13
90 // r/w 32 bit - Watchpoint 0 Address
91 #define EICE_WP1ADDR 16
92 // r/w 32 bit - Watchpoint 0 Addres Mask
93 #define EICE_WP1ADDRMASK 17
94 // r/w 32 bit - Watchpoint 0 Data
95 #define EICE_WP1DATA 18
96 // r/w 32 bit - Watchpoint 0 Data Masl
97 #define EICE_WP1DATAMASK 19
98 // r/w 9 bit - Watchpoint 0 Control Value
99 #define EICE_WP1CTRL 20
100 // r/w 8 bit - Watchpoint 0 Control Mask
101 #define EICE_WP1CTRLMASK 21
104 //JTAGARM7TDMI commands
105 #define JTAGARM7_GET_REGISTER 0x87
106 #define JTAGARM7_SET_REGISTER 0x88
107 #define JTAGARM7_DEBUG_INSTR 0x89
108 // Really ARM specific stuff
109 #define JTAGARM7_SET_IR 0x90
110 #define JTAGARM7_WAIT_DBG 0x91
111 #define JTAGARM7_SHIFT_DR 0x92
112 #define JTAGARM7_CHAIN0 0x93
113 #define JTAGARM7_SCANCHAIN1 0x94
114 #define JTAGARM7_EICE_READ 0x95
115 #define JTAGARM7_EICE_WRITE 0x96
118 // for deeper understanding, read the instruction cycle timing section of:
119 // http://www.atmel.com/dyn/resources/prod_documents/DDI0029G_7TDMI_R3_trm.pdf
120 #define EXECNOPARM 0xe1a00000L
121 #define ARM_INSTR_NOP 0xe1a00000L
122 #define ARM_INSTR_BX_R0 0xe12fff10L
123 #define ARM_INSTR_STR_Rx_r14 0xe58f0000L // from atmel docs
124 #define ARM_READ_REG ARM_INSTR_STR_Rx_r14
125 #define ARM_INSTR_LDR_Rx_r14 0xe5900000L // NOT from atmel docs (e59e0000L is from atmel docs)
126 #define ARM_WRITE_REG ARM_INSTR_LDR_Rx_r14
127 #define ARM_INSTR_LDR_R1_r0_4 0xe4901004L
128 #define ARM_READ_MEM ARM_INSTR_LDR_R1_r0_4
129 #define ARM_INSTR_STR_R1_r0_4 0xe4801004L
130 #define ARM_WRITE_MEM ARM_INSTR_STR_R1_r0_4
131 #define ARM_INSTR_MRS_R0_CPSR 0xe10f0000L
132 #define ARM_INSTR_MSR_cpsr_cxsf_R0 0xe12ff000L
133 #define ARM_INSTR_STMIA_R14_r0_rx 0xE88E0000L // add up to 65k to indicate which registers...
134 #define ARM_STORE_MULTIPLE ARM_INSTR_STMIA_R14_r0_rx
135 #define ARM_INSTR_SKANKREGS 0xE88F7fffL
136 #define ARM_INSTR_CLOBBEREGS 0xE89F7fffL
138 #define ARM_INSTR_B_IMM 0xea000000L
139 #define ARM_INSTR_BX_PC 0xe12fff10L // need to set r0 to the desired address
140 #define THUMB_INSTR_LDR_R0_r0 0x68006800L
141 #define THUMB_WRITE_REG THUMB_INSTR_LDR_R0_r0
142 #define THUMB_INSTR_STR_R0_r0 0x60006000L
143 #define THUMB_READ_REG THUMB_INSTR_STR_R0_r0
144 #define THUMB_INSTR_MOV_R0_PC 0x46b846b8L
145 #define THUMB_INSTR_MOV_PC_R0 0x46474647L
146 #define THUMB_INSTR_MOV_HiLo 0x46404640L
147 #define THUMB_INSTR_MOV_LoHi 0x46804680L
148 #define THUMB_INSTR_BX_PC 0x47784778L
149 #define THUMB_INSTR_NOP 0x1c001c00L
150 #define THUMB_SWAP_HiLo 0
151 #define THUMB_SWAP_LoHi 1
152 #define ARM_REG_PC 15
154 #define JTAG_ARM7TDMI_DBG_DBGACK 1
155 #define JTAG_ARM7TDMI_DBG_DBGRQ 2
156 #define JTAG_ARM7TDMI_DBG_IFEN 4
157 #define JTAG_ARM7TDMI_DBG_cgenL 8
158 #define JTAG_ARM7TDMI_DBG_TBIT 16
160 extern app_t const jtagarm7_app;