1 //! MSP430F1612/1611 clock and I/O definitions
14 unsigned char serial0_rx(){
17 while(!(IFG1&URXIFG0));//wait for a byte
26 unsigned char serial1_rx(){
29 while(!(IFG2&URXIFG1));//wait for a byte
38 void serial0_tx(unsigned char x){
39 while ((IFG1 & UTXIFG0) == 0); //loop until buffer is free
43 //! Transmit a byte on the second UART.
44 void serial1_tx(unsigned char x){
45 while ((IFG2 & UTXIFG1) == 0); //loop until buffer is free
49 /** Later, add support for the EZ430/FETUIF with 12MHz crystal
50 UBR00=0xE2; UBR10=0x04; UMCTL0=0x00; // uart0 12000000Hz 9600bps
51 UBR00=0x71; UBR10=0x02; UMCTL0=0x00; // uart0 12000000Hz 19200bps
52 UBR00=0x38; UBR10=0x01; UMCTL0=0x55; // uart0 12000000Hz 38400bps
53 UBR00=0xD0; UBR10=0x00; UMCTL0=0x4A; // uart0 12000000Hz 57581bps
54 UBR00=0x68; UBR10=0x00; UMCTL0=0x04; // uart0 12000000Hz 115273bps
57 //! Set the baud rate.
58 void setbaud0(unsigned char rate){
60 //http://mspgcc.sourceforge.net/baudrate.html
63 UBR00=0x7F; UBR10=0x01; UMCTL0=0x5B; /* uart0 3683400Hz 9599bps */
66 UBR00=0xBF; UBR10=0x00; UMCTL0=0xF7; /* uart0 3683400Hz 19194bps */
69 UBR00=0x5F; UBR10=0x00; UMCTL0=0xBF; /* uart0 3683400Hz 38408bps */
72 UBR00=0x40; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 57553bps */
76 UBR00=0x20; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 115106bps */
81 //! Set the baud rate of the second uart.
82 void setbaud1(unsigned char rate){
83 //http://mspgcc.sourceforge.net/baudrate.html
86 UBR01=0x7F; UBR11=0x01; UMCTL1=0x5B; /* uart0 3683400Hz 9599bps */
89 UBR01=0xBF; UBR11=0x00; UMCTL1=0xF7; /* uart0 3683400Hz 19194bps */
92 UBR01=0x5F; UBR11=0x00; UMCTL1=0xBF; /* uart0 3683400Hz 38408bps */
95 UBR01=0x40; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 57553bps */
99 UBR01=0x20; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 115106bps */
105 void msp430_init_uart0(){
108 P3SEL |= BIT4|BIT5; // P3.4,5 = USART0 TXD/RXD
111 UCTL0 = SWRST | CHAR; /* 8-bit character, UART mode */
112 UTCTL0 = SSEL1; /* UCLK = MCLK */
116 ME1 &= ~USPIE0; /* USART1 SPI module disable */
117 ME1 |= (UTXE0 | URXE0); /* Enable USART1 TXD/RXD */
121 /* XXX Clear pending interrupts before enable!!! */
125 //IE1 |= URXIE1; /* Enable USART1 RX interrupt */
129 void msp430_init_uart1(){
132 P3DIR &= ~0x80; /* Select P37 for input (UART1RX) */
133 P3DIR |= 0x40; /* Select P36 for output (UART1TX) */
134 P3SEL |= 0xC0; /* Select P36,P37 for UART1{TX,RX} */
136 UCTL1 = SWRST | CHAR; /* 8-bit character, UART mode */
137 UTCTL1 = SSEL1; /* UCLK = MCLK */
141 ME2 &= ~USPIE1; /* USART1 SPI module disable */
142 ME2 |= (UTXE1 | URXE1); /* Enable USART1 TXD/RXD */
146 /* XXX Clear pending interrupts before enable!!! */
149 //IE2 |= URXIE1; /* Enable USART1 RX interrupt */
154 void msp430_init_dco() {
155 WDTCTL = WDTPW + WDTHOLD; //stop WDT
162 for (i=0; i<1000; i++);
164 } while (IFG1 & OFIFG);
166 BCSCTL2 = SELM1 | DIVM1 | SELS;
172 //! Initialization is correct.
173 void msp430_init_dco_done(){
174 //Nothing to do for the 1612.
178 void msp430_init_dco() {
179 /* This code taken from the FU Berlin sources and reformatted. */
183 //#define MSP430_CPU_SPEED 2457600UL
185 //Too fast for internal resistor.
186 //#define MSP430_CPU_SPEED 4915200UL
189 //#define MSP430_CPU_SPEED 4500000UL
192 #define MSP430_CPU_SPEED 3683400UL
193 #define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
194 unsigned int compare, oldcapture = 0;
197 WDTCTL = WDTPW + WDTHOLD; //stop WDT
204 /* ACLK is devided by 4. RSEL=6 no division for MCLK
205 and SSMCLK. XT2 is off. */
208 BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
209 crystal DCO frquenzy = 2,4576 MHz */
213 BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
214 for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
218 CCTL2 = CCIS0 + CM0 + CAP; // Define CCR2, CAP, ACLK
219 TACTL = TASSEL1 + TACLR + MC1; // SMCLK, continous mode
224 while((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured! */
225 CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
226 compare = CCR2; /* Get current captured SMCLK */
227 compare = compare - oldcapture; /* SMCLK difference */
228 oldcapture = CCR2; /* Save current captured SMCLK */
230 if(DELTA == compare) {
231 break; /* if equal, leave "while(1)" */
232 } else if(DELTA < compare) { /* DCO is too fast, slow it down */
234 if(DCOCTL == 0xFF) { /* Did DCO role under? */
237 } else { /* -> Select next lower RSEL */
239 if(DCOCTL == 0x00) { /* Did DCO role over? */
242 /* -> Select next higher RSEL */
246 CCTL2 = 0; /* Stop CCR2 function */
247 TACTL = 0; /* Stop Timer_A */
249 BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */