void glitchsetup(){
#ifdef DAC12IR
//Set GSEL high to disable glitching.
-
- P5DIR|=0x80;
- P6DIR|=BIT6+BIT5;
- P5OUT|=0x80;
+ //Normal voltage, use resistors instead of output.
+ //P5DIR=0x80; //ONLY glitch pin is output.
+ P5OUT|=0x80; //It MUST begin high.
+ //P5REN|=0x7F; //Resistors pull high and low weakly.
+
+ P6DIR|=BIT6+BIT5;
P6OUT|=BIT6+BIT5;
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
TACTL = TASSEL1 + TACLR; // SMCLK, clear TAR
CCTL0 = CCIE; // CCR0 interrupt enabled
- CCR0 = glitchcount+0x30; //clock divider
- TACTL |= MC_3;
- _EINT(); // Enable interrupts
+ CCR0 = glitchcount+0x15; // Compare Value
+ TACTL |= MC_2; // continuous mode.
#endif
}
// Timer A0 interrupt service routine
-interrupt(TIMERA0_VECTOR) Timer_A (void)
-{
- P1OUT^=1;
+interrupt(TIMERA0_VECTOR) Timer_A (void){
P5OUT&=~BIT7;//Glitch
+ //P5DIR=BIT7; //All else high impedance.
P5OUT|=BIT7;//Normal
TACTL |= MC0;// Stop Timer_A;
- P1OUT&=~1;
return;
}
//debughex(gnd);
//debughex(vcc);
+ /** N.B., because this is confusing as hell. As per Page 86 of
+ SLAS541F, P6SEL is not what controls the use of the DAC0/DAC1
+ functions on P6.6 and P6.5. Instead, CAPD or DAC12AMP>0 sets
+ the state.
+ */
+
#ifdef DAC12IR
ADC12CTL0 = REF2_5V + REFON; // Internal 2.5V ref on
// Delay here for reference to settle.
TACTL=0; //clear dividers
TACTL|=TACLR; //clear config
TACTL|=TASSEL_SMCLK| //smclk source
- MC_2; //continuout mode.
+ MC_2; //continuous mode.
//perform the function
silent++;//Don't want the function to return anything.
txdata(app,verb,2);
break;
case START:
+ //Testing mode, for looking at the glitch waveform.
glitchvoltages(0xFFF,0);//Inverted VCC and GND.
P5OUT|=BIT7;//Normal
P5DIR|=BIT7;