2 \author Travis Goodspeed
3 \brief Chipcon 8051 debugging.
7 //This is like SPI, except that you read or write, not both.
9 /* N.B. The READ verb performs a write of all (any) supplied data,
10 then reads a single byte reply from the target. The WRITE verb
23 /* Concerning clock rates, the maximimum clock rates are defined on
24 page 4 of the spec. They vary, but are roughly 30MHz. Raising
25 this clock rate might allow for clock glitching, but the GoodFET
26 isn't sufficient fast for that. Perhaps a 200MHz ARM or an FPGA in
31 //MISO and MOSI are the same pin, direction changes.
37 //This could be more accurate.
38 //Does it ever need to be?
40 //#define CCDELAY(x) delay(x)
43 #define SETMOSI P5OUT|=MOSI
44 #define CLRMOSI P5OUT&=~MOSI
45 #define SETCLK P5OUT|=SCK
46 #define CLRCLK P5OUT&=~SCK
47 #define READMISO (P5IN&MISO?1:0)
49 #define CCWRITE P5DIR|=MOSI
50 #define CCREAD P5DIR&=~MISO
52 //! Set up the pins for CC mode. Does not init debugger.
59 //! Initialize the debugger
61 //Port output BUT NOT DIRECTION is set at start.
64 //delay(30); //So the beginning is ready for glitching.
66 //Two positive debug clock pulses while !RST is low.
67 //Take RST low, pulse twice, then high.
75 P5OUT^=SCK; //Unnecessary.
82 //! Read and write a CC bit.
83 unsigned char cctrans8(unsigned char byte){
85 //This function came from the SPI Wikipedia article.
88 for (bit = 0; bit < 8; bit++) {
89 /* write MOSI on trailing edge of previous clock */
96 /* half a clock cycle before leading/rising edge */
100 /* half a clock cycle before trailing/falling edge */
103 /* read MISO on trailing edge */
111 //! Send a command from txbytes.
112 void cccmd(unsigned char len){
116 cctrans8(cmddata[i]);
119 //! Fetch a reply, usually 1 byte.
120 void ccread(unsigned char len){
124 cmddata[i]=cctrans8(0);
127 //! Handles a monitor command.
128 void cchandle(unsigned char app,
131 //Always init. Might help with buggy lines.
137 //CC_PEEK and CC_POKE will come later.
139 cmddata[0]=cc_peekirambyte(cmddata[0]);
143 cmddata[0]=cc_pokeirambyte(cmddata[0],cmddata[1]);
146 case READ: //Write a command and return 1-byte reply.
152 case WRITE: //Write a command with no reply.
156 case START://enter debugger
160 case STOP://exit debugger
161 //Take RST low, then high.
178 cc_wr_config(cmddata[0]);
191 //no break, return status
196 case CC_SET_HW_BRKPNT:
197 cc_set_hw_brkpnt(cmddataword[0]);
216 case CC_STEP_REPLACE:
217 txdata(app,NOK,0);//TODO add me
220 cmddataword[0]=cc_get_chip_id();
226 case CC_READ_CODE_MEMORY:
227 cmddata[0]=cc_peekcodebyte(cmddataword[0]);
230 case CC_READ_XDATA_MEMORY:
231 cmddata[0]=cc_peekdatabyte(cmddataword[0]);
234 case CC_WRITE_XDATA_MEMORY:
235 cmddata[0]=cc_pokedatabyte(cmddataword[0], cmddata[2]);
239 cc_set_pc(cmddatalong[0]);
242 case CC_WRITE_FLASH_PAGE:
243 cc_write_flash_page(cmddatalong[0]);
246 case CC_WIPEFLASHBUFFER:
247 for(i=0xf000;i<0xf800;i++)
248 cc_pokedatabyte(i,0xFF);
251 case CC_MASS_ERASE_FLASH:
253 case CC_PROGRAM_FLASH:
254 debugstr("This Chipcon command is not yet implemented.");
255 txdata(app,NOK,0);//TODO implement me.
260 //! Set the Chipcon's Program Counter
261 void cc_set_pc(u32 adr){
262 cmddata[0]=0x02; //SetPC
263 cmddata[1]=((adr>>8)&0xff); //HIBYTE
264 cmddata[2]=adr&0xff; //LOBYTE
269 //! Erase all of a Chipcon's memory.
270 void cc_chip_erase(){
271 cmddata[0]=CCCMD_CHIP_ERASE; //0x14
275 //! Write the configuration byte.
276 void cc_wr_config(unsigned char config){
277 cmddata[0]=CCCMD_WR_CONFIG; //0x1D
287 //debugstr("Locking chip.");
288 cc_wr_config(1);//Select Info Flash
289 if(!(cc_rd_config()&1))
290 debugstr("Config forgotten!");
294 cc_pokedatabyte(0xf000+i,0);
295 cc_write_flash_page(0);
296 if(cc_peekcodebyte(0))
297 debugstr("Failed to clear info flash byte.");
301 debugstr("Stuck in info flash mode!");
304 //! Read the configuration byte.
305 unsigned char cc_rd_config(){
306 cmddata[0]=CCCMD_RD_CONFIG; //0x24
313 //! Read the status register
314 unsigned char cc_read_status(){
315 cmddata[0]=CCCMD_READ_STATUS; //0x3f
321 //! Read the CHIP ID bytes.
322 unsigned short cc_get_chip_id(){
323 cmddata[0]=CCCMD_GET_CHIP_ID; //0x68
328 //Find the flash word size.
333 flash_word_size=0x02;
334 //debugstr("2 bytes/flash word");
337 debugstr("Warning: Guessing flash word size.");
340 //debugstr("4 bytes/flash word");
341 flash_word_size=0x04;
346 return cmddataword[0];
349 //! Populates flash buffer in xdata.
350 void cc_write_flash_buffer(u8 *data, u16 len){
351 cc_write_xdata(0xf000, data, len);
353 //! Populates flash buffer in xdata.
354 void cc_write_xdata(u16 adr, u8 *data, u16 len){
356 for(i=0; i<len; i++){
357 cc_pokedatabyte(adr+i,
363 //32-bit words, 2KB pages
364 //0x20 0x00 for CC2430, CC1110
365 #define HIBYTE_WORDS_PER_FLASH_PAGE 0x02
366 #define LOBYTE_WORDS_PER_FLASH_PAGE 0x00
368 /** Ugh, this varies by chip.
372 //#define FLASHPAGE_SIZE 0x400
373 #define MAXFLASHPAGE_SIZE 0x800
374 #define MINFLASHPAGE_SIZE 0x400
377 //32 bit words on CC2430
378 //16 bit words on CC1110
379 //#define FLASH_WORD_SIZE 0x2
380 u8 flash_word_size = 0; //0x02;
383 /* Flash Write Timing
390 32 | 0x2A (Modula.si)
394 const u8 flash_routine[] = {
398 0x00,//#imm=((address >> 8) / FLASH_WORD_SIZE) & 0x7E,
400 //0x75, 0xAB, 0x23, //Set FWT per clock
401 0x75, 0xAC, 0x00, // MOV FADDRL, #00;
403 0x75, 0xAE, 0x01, // MOV FLC, #01H; // ERASE
404 // ; Wait for flash erase to complete
405 0xE5, 0xAE, // eraseWaitLoop: MOV A, FLC;
406 0x20, 0xE7, 0xFB, // JB ACC_BUSY, eraseWaitLoop;
408 /* End erase page. */
409 // ; Initialize the data pointer
410 0x90, 0xF0, 0x00, // MOV DPTR, #0F000H;
412 0x7F, HIBYTE_WORDS_PER_FLASH_PAGE, // MOV R7, #imm;
413 0x7E, LOBYTE_WORDS_PER_FLASH_PAGE, // MOV R6, #imm;
414 0x75, 0xAE, 0x02, // MOV FLC, #02H; // WRITE
417 0x7D, 0xde /*FLASH_WORD_SIZE*/, // writeLoop: MOV R5, #imm;
418 0xE0, // writeWordLoop: MOVX A, @DPTR;
420 0xF5, 0xAF, // MOV FWDATA, A;
421 0xDD, 0xFA, // DJNZ R5, writeWordLoop;
422 // ; Wait for completion
423 0xE5, 0xAE, // writeWaitLoop: MOV A, FLC;
424 0x20, 0xE6, 0xFB, // JB ACC_SWBSY, writeWaitLoop;
425 0xDE, 0xF1, // DJNZ R6, writeLoop;
426 0xDF, 0xEF, // DJNZ R7, writeLoop;
427 // ; Done, fake a breakpoint
432 //! Copies flash buffer to flash.
433 void cc_write_flash_page(u32 adr){
434 //Assumes that page has already been written to XDATA 0xF000
435 //debugstr("Flashing 2kb at 0xF000 to given adr.");
437 if(adr&(MINFLASHPAGE_SIZE-1)){
438 debugstr("Flash page address is not on a page boundary. Aborting.");
442 if(flash_word_size==0){
443 debugstr("Flash word size is wrong.");
448 //WRITE_XDATA_MEMORY(IN: 0xF000 + FLASH_PAGE_SIZE, sizeof(routine), routine);
449 cc_write_xdata(0xF000+MAXFLASHPAGE_SIZE,
450 (u8*) flash_routine, sizeof(flash_routine));
451 //Patch routine's third byte with
452 //((address >> 8) / FLASH_WORD_SIZE) & 0x7E
453 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+2,
454 ((adr>>8)/flash_word_size)&0x7E);
455 //Patch routine to define FLASH_WORD_SIZE
456 if(flash_routine[25]!=0xde)
457 debugstr("Ugly patching code failing in chipcon.c");
458 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+25,
461 //debugstr("Wrote flash routine.");
464 //MOV MEMCTR, (bank * 16) + 1;
469 //debugstr("Loaded bank info.");
471 cc_set_pc(0xf000+MAXFLASHPAGE_SIZE);//execute code fragment
474 //debugstr("Executing.");
477 while(!(cc_read_status()&CC_STATUS_CPUHALTED)){
478 P1OUT^=1;//blink LED while flashing
482 //debugstr("Done flashing.");
484 P1OUT&=~1;//clear LED
488 unsigned short cc_get_pc(){
489 cmddata[0]=CCCMD_GET_PC; //0x28
494 return cmddataword[0];
497 //! Set a hardware breakpoint.
498 void cc_set_hw_brkpnt(unsigned short adr){
499 debugstr("FIXME: This certainly won't work.");
509 cmddata[0]=CCCMD_HALT; //0x44
516 cmddata[0]=CCCMD_RESUME; //0x4C
523 //! Step an instruction
524 void cc_step_instr(){
525 cmddata[0]=CCCMD_STEP_INSTR; //0x5C
531 //! Debug an instruction.
532 void cc_debug_instr(unsigned char len){
533 //Bottom two bits of command indicate length.
534 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3); //0x54+len
536 cctrans8(cmd); //Second command code
537 cccmd(len&0x3); //Command itself.
542 //! Debug an instruction, for local use.
543 unsigned char cc_debug(unsigned char len,
547 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3);//0x54+len
557 return cctrans8(0x00);
560 //! Fetch a byte of code memory.
561 unsigned char cc_peekcodebyte(unsigned long adr){
562 /** See page 9 of SWRA124 */
563 unsigned char bank=adr>>15,
569 //MOV MEMCTR, (bank*16)+1
570 cc_debug(3, 0x75, 0xC7, (bank<<4) + 1);
572 cc_debug(3, 0x90, hb, lb);
576 cc_debug(2, 0xE4, 0, 0);
578 toret=cc_debug(3, 0x93, 0, 0);
580 //cc_debug(1, 0xA3, 0, 0);
586 //! Set a byte of data memory.
587 unsigned char cc_pokedatabyte(unsigned int adr,
594 cc_debug(3, 0x90, hb, lb);
596 cc_debug(2, 0x74, val, 0);
598 cc_debug(1, 0xF0, 0, 0);
602 DEBUG_INSTR(IN: 0x90, HIBYTE(address), LOBYTE(address), OUT: Discard);
603 for (n = 0; n < count; n++) {
604 DEBUG_INSTR(IN: 0x74, inputArray[n], OUT: Discard);
605 DEBUG_INSTR(IN: 0xF0, OUT: Discard);
606 DEBUG_INSTR(IN: 0xA3, OUT: Discard);
611 //! Fetch a byte of data memory.
612 unsigned char cc_peekdatabyte(unsigned int adr){
618 cc_debug(3, 0x90, hb, lb);
620 //Must be 2, perhaps for clocking?
621 return cc_debug(3, 0xE0, 0, 0);
625 //! Fetch a byte of IRAM.
626 u8 cc_peekirambyte(u8 adr){
628 cc_debug(2, 0xE4, 0, 0);
630 return cc_debug(3, 0xE5, adr, 0);
633 //! Write a byte of IRAM.
634 u8 cc_pokeirambyte(u8 adr, u8 val){
636 cc_debug(2, 0xE4, 0, 0);
638 return cc_debug(3, 0x75, adr, val);
639 //return cc_debug(3, 0x75, val, adr);