2 \author Travis Goodspeed <travis at radiantmachines.com>
3 \brief MSP430 JTAG (16-bit)
10 //! Handles classic MSP430 JTAG commands. Forwards others to JTAG.
11 void jtag430_handle_fn(uint8_t const app,
15 // define the jtag430 app's app_t
16 app_t const jtag430_app = {
27 "\tThe JTAG430 app adds to the basic JTAG app\n"
28 "\tsupport for JTAG'ing MSP430 devices.\n"
31 unsigned int jtag430mode=MSP430X2MODE;
34 void jtag430_setr(u8 reg, u16 val){
35 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
36 jtag_dr_shift16(0x3401);// release low byte
37 jtag_ir_shift8(IR_DATA_16BIT);
39 //0x4030 is "MOV #foo, r0"
40 //Right-most field is register, so 0x4035 loads r5
41 jtag_dr_shift16(0x4030+reg);
44 jtag_dr_shift16(val);// Value for the register
46 jtag_ir_shift8(IR_ADDR_CAPTURE);
48 CLRTCLK ;// Now reg is set to new value.
49 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
50 jtag_dr_shift16(0x2401);// low byte controlled by JTAG
53 //! Set the program counter.
54 void jtag430_setpc(unsigned int adr){
59 void jtag430_haltcpu(){
60 //jtag430_setinstrfetch();
62 jtag_ir_shift8(IR_DATA_16BIT);
63 jtag_dr_shift16(0x3FFF);//JMP $+0
66 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
67 jtag_dr_shift16(0x2409);//set JTAG_HALT bit
72 void jtag430_releasecpu(){
74 //debugstr("Releasing target MSP430.");
77 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
78 jtag_dr_shift16(0x2C01); //Apply reset.
79 jtag_dr_shift16(0x2401); //Release reset.
81 jtag_ir_shift8(IR_CNTRL_SIG_RELEASE);
85 //! Read data from address
86 unsigned int jtag430_readmem(unsigned int adr){
91 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
94 jtag_dr_shift16(0x2409);//word read
96 jtag_dr_shift16(0x2419);//byte read
97 jtag_ir_shift8(IR_ADDR_16BIT);
98 jtag_dr_shiftadr(adr);//address
99 jtag_ir_shift8(IR_DATA_TO_ADDR);
103 toret=jtag_dr_shift16(0x0000);//16 bit return
108 //! Write data to address.
109 void jtag430_writemem(unsigned int adr, unsigned int data){
111 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
113 jtag_dr_shift16(0x2408);//word write
115 jtag_dr_shift16(0x2418);//byte write
116 jtag_ir_shift8(IR_ADDR_16BIT);
117 jtag_dr_shiftadr(adr);
118 jtag_ir_shift8(IR_DATA_TO_ADDR);
119 jtag_dr_shift16(data);
123 //! Write data to flash memory. Must be preconfigured.
124 void jtag430_writeflashword(unsigned int adr, unsigned int data){
127 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
128 jtag_dr_shift16(0x2408);//word write
129 jtag_ir_shift8(IR_ADDR_16BIT);
130 jtag_dr_shiftadr(adr);
131 jtag_ir_shift8(IR_DATA_TO_ADDR);
132 jtag_dr_shift16(data);
135 //Return to read mode.
137 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
138 jtag_dr_shift16(0x2409);
141 jtag430_writemem(adr,data);
143 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
144 jtag_dr_shift16(0x2409);
148 jtag430_tclk_flashpulses(35); //35 standard
151 //! Configure flash, then write a word.
152 void jtag430_writeflash(unsigned int adr, unsigned int data){
155 //FCTL1=0xA540, enabling flash write
156 jtag430_writemem(0x0128, 0xA540);
157 //FCTL2=0xA540, selecting MCLK as source, DIV=1
158 jtag430_writemem(0x012A, 0xA540);
159 //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
160 jtag430_writemem(0x012C, 0xA500); //all but info flash.
161 //if(jtag430_readmem(0x012C));
163 //Write the word itself.
164 jtag430_writeflashword(adr,data);
166 //FCTL1=0xA500, disabling flash write
167 jtag430_writemem(0x0128, 0xA500);
169 //jtag430_releasecpu();
177 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
178 jtag_dr_shift16(0x2C01); // apply
179 jtag_dr_shift16(0x2401); // remove
185 jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
188 jtag430_writemem(0x0120, 0x5A80); // Diabled Watchdog
193 #define ERASE_GLOB 0xA50E
194 #define ERASE_ALLMAIN 0xA50C
195 #define ERASE_MASS 0xA506
196 #define ERASE_MAIN 0xA504
197 #define ERASE_SGMT 0xA502
199 //! Configure flash, then write a word.
200 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count,
205 jtag430_writemem(0x0128, mode);
206 //FCTL2=0xA540, selecting MCLK as source, DIV=1
207 jtag430_writemem(0x012A, 0xA540);
208 //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
210 jtag430_writemem(0x012C, 0xA540);
212 jtag430_writemem(0x012C, 0xA500);
214 //Write the erase word.
215 jtag430_writemem(adr, 0x55AA);
216 //Return to read mode.
218 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
219 jtag_dr_shift16(0x2409);
222 jtag430_tclk_flashpulses(count);
224 //FCTL1=0xA500, disabling flash write
225 jtag430_writemem(0x0128, 0xA500);
227 //jtag430_releasecpu();
231 //! Reset the TAP state machine.
232 void jtag430_resettap(){
240 // Navigate to reset state.
241 // Should be at least six.
254 Sometimes this isn't necessary. */
268 unsigned char jtag430x2_jtagid(){
270 jtagid=jtag_ir_shift8(IR_BYPASS);
271 if(jtagid!=0x89 && jtagid!=0x91){
272 debugstr("Unknown JTAG ID");
277 //! Start JTAG, take pins
278 unsigned char jtag430x2_start(){
281 //Known-good starting position.
282 //Might be unnecessary.
288 //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
301 //Perform a reset and disable watchdog.
302 return jtag430x2_jtagid();
306 //! Start JTAG, take pins
307 void jtag430_start(){
310 //Known-good starting position.
311 //Might be unnecessary.
318 //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
330 //Perform a reset and disable watchdog.
332 jtag430_writemem(0x120,0x5a80);//disable watchdog
339 debugstr("Exiting JTAG.");
342 //Known-good starting position.
343 //Might be unnecessary.
349 //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
358 //! Set CPU to Instruction Fetch
359 void jtag430_setinstrfetch(){
361 jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
363 // Wait until instruction fetch state.
365 if (jtag_dr_shift16(0x0000) & 0x0080)
376 //! Handles classic MSP430 JTAG commands. Forwards others to JTAG.
377 void jtag430_handle_fn(uint8_t const app,
386 * Sometimes JTAG doesn't init correctly.
387 * This restarts the connection if the masked-rom
388 * chip ID cannot be read. Should print warning
389 * for testing server.
392 while((i=jtag430_readmem(0xff0))==0xFFFF){
393 debugstr("Reconnecting to target MSP430.");
402 debugstr("Using JTAG430 (instead of JTAG430X2)!");
407 jtag430mode=MSP430MODE;
409 /* So the way this works is that a width of 20 does some
410 backward-compatibility finagling, causing the correct value
411 to be exchanged for addresses on 16-bit chips as well as the
412 new MSP430X chips. (This has only been verified on the
413 MSP430F2xx family. TODO verify for others.)
418 //Perform a reset and disable watchdog.
420 jtag430_writemem(0x120,0x5a80);//disable watchdog
432 case JTAG430_HALTCPU:
436 case JTAG430_RELEASECPU:
437 jtag430_releasecpu();
440 case JTAG430_SETINSTRFETCH:
441 jtag430_setinstrfetch();
445 case JTAG430_READMEM:
449 //Fetch large blocks for bulk fetches,
450 //small blocks for individual peeks.
452 l=(cmddataword[2]);//always even.
458 for(i = 0; i < l; i += 2) {
460 val=jtag430_readmem(at);
464 serial_tx((val&0xFF00)>>8);
467 case JTAG430_WRITEMEM:
470 jtag430_writemem(cmddataword[0],cmddataword[2]);
471 cmddataword[0]=jtag430_readmem(cmddataword[0]);
474 case JTAG430_WRITEFLASH:
477 for(i=0;i<(len>>1)-2;i++){
478 //debugstr("Poking flash memory.");
479 jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
480 //Reflash if needed. Try this twice to save grace?
481 if(cmddataword[i]!=jtag430_readmem(at))
482 jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
485 //Return result of first write as a word.
486 cmddataword[0]=jtag430_readmem(cmddataword[0]);
490 case JTAG430_ERASEFLASH:
491 jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000,0);
494 case JTAG430_ERASEINFO:
495 jtag430_eraseflash(ERASE_SGMT,0x1000,0x3000,1);
500 //debughex("Setting PC.");
501 //debughex(cmddataword[0]);
502 jtag430_setpc(cmddataword[0]);
503 jtag430_releasecpu();
507 jtag430_setr(cmddata[0],cmddataword[1]);
511 //jtag430_getr(cmddata[0]);
512 debugstr("JTAG430_GETREG not yet implemented.");
513 cmddataword[0]=0xDEAD;
516 case JTAG430_COREIP_ID:
517 //cmddataword[0]=jtag430_coreid();
518 cmddataword[0]=0xdead;
521 case JTAG430_DEVICE_ID:
522 //cmddatalong[0]=jtag430_deviceid();
523 cmddataword[0]=0xdead;
524 cmddataword[1]=0xbeef;
528 (*(jtag_app.handle))(app,verb,len);
530 //jtag430_resettap(); //DO NOT UNCOMMENT