2 * linux/arch/alpha/kernel/core_marvel.c
4 * Code common to all Marvel based systems.
7 #include <linux/config.h>
9 #define __EXTERN_INLINE inline
11 #include <asm/core_marvel.h>
12 #undef __EXTERN_INLINE
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/pci.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/vmalloc.h>
20 #include <linux/mc146818rtc.h>
22 #include <asm/ptrace.h>
23 #include <asm/system.h>
25 #include <asm/hwrpb.h>
27 #include <asm/pgalloc.h>
29 #include <linux/bootmem.h>
38 #define DEBUG_CONFIG 0
41 # define DBG_CFG(args) printk args
43 # define DBG_CFG(args)
50 static struct io7 *io7_head = NULL;
56 static unsigned long __attribute__ ((unused))
57 read_ev7_csr(int pe, unsigned long offset)
59 ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset);
69 static void __attribute__ ((unused))
70 write_ev7_csr(int pe, unsigned long offset, unsigned long q)
72 ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset);
80 mk_resource_name(int pe, int port, char *str)
85 sprintf(tmp, "PCI %s PE %d PORT %d", str, pe, port);
86 name = alloc_bootmem(strlen(tmp) + 1);
93 marvel_next_io7(struct io7 *prev)
95 return (prev ? prev->next : io7_head);
99 marvel_find_io7(int pe)
103 for (io7 = io7_head; io7 && io7->pe != pe; io7 = io7->next)
109 static struct io7 * __init
110 alloc_io7(unsigned int pe)
116 if (marvel_find_io7(pe)) {
117 printk(KERN_WARNING "IO7 at PE %d already allocated!\n", pe);
121 io7 = alloc_bootmem(sizeof(*io7));
123 io7->irq_lock = SPIN_LOCK_UNLOCKED;
125 for (h = 0; h < 4; h++) {
126 io7->ports[h].io7 = io7;
127 io7->ports[h].port = h;
128 io7->ports[h].enabled = 0; /* default to disabled */
132 * Insert in pe sorted order.
134 if (NULL == io7_head) /* empty list */
136 else if (io7_head->pe > io7->pe) { /* insert at head */
137 io7->next = io7_head;
139 } else { /* insert at position */
140 for (insp = io7_head; insp; insp = insp->next) {
141 if (insp->pe == io7->pe) {
142 printk(KERN_ERR "Too many IO7s at PE %d\n",
147 if (NULL == insp->next ||
148 insp->next->pe > io7->pe) { /* insert here */
149 io7->next = insp->next;
155 if (NULL == insp) { /* couldn't insert ?!? */
156 printk(KERN_WARNING "Failed to insert IO7 at PE %d "
157 " - adding at head of list\n", io7->pe);
158 io7->next = io7_head;
167 io7_clear_errors(struct io7 *io7)
169 io7_port7_csrs *p7csrs;
170 io7_ioport_csrs *csrs;
175 * First the IO ports.
177 for (port = 0; port < 4; port++) {
178 csrs = IO7_CSRS_KERN(io7->pe, port);
180 csrs->POx_ERR_SUM.csr = -1UL;
181 csrs->POx_TLB_ERR.csr = -1UL;
182 csrs->POx_SPL_COMPLT.csr = -1UL;
183 csrs->POx_TRANS_SUM.csr = -1UL;
187 * Then the common ones.
189 p7csrs = IO7_PORT7_CSRS_KERN(io7->pe);
191 p7csrs->PO7_ERROR_SUM.csr = -1UL;
192 p7csrs->PO7_UNCRR_SYM.csr = -1UL;
193 p7csrs->PO7_CRRCT_SYM.csr = -1UL;
198 * IO7 PCI, PCI/X, AGP configuration.
201 io7_init_hose(struct io7 *io7, int port)
203 static int hose_index = 0;
205 struct pci_controller *hose = alloc_pci_controller();
206 struct io7_port *io7_port = &io7->ports[port];
207 io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, port);
210 hose->index = hose_index++; /* arbitrary */
213 * We don't have an isa or legacy hose, but glibc expects to be
214 * able to use the bus == 0 / dev == 0 form of the iobase syscall
215 * to determine information about the i/o system. Since XFree86
216 * relies on glibc's determination to tell whether or not to use
217 * sparse access, we need to point the pci_isa_hose at a real hose
218 * so at least that determination is correct.
220 if (hose->index == 0)
223 io7_port->csrs = csrs;
224 io7_port->hose = hose;
225 hose->sysdata = io7_port;
227 hose->io_space = alloc_resource();
228 hose->mem_space = alloc_resource();
231 * Base addresses for userland consumption. Since these are going
232 * to be mapped, they are pure physical addresses.
234 hose->sparse_mem_base = hose->sparse_io_base = 0;
235 hose->dense_mem_base = IO7_MEM_PHYS(io7->pe, port);
236 hose->dense_io_base = IO7_IO_PHYS(io7->pe, port);
239 * Base addresses and resource ranges for kernel consumption.
241 hose->config_space_base = (unsigned long)IO7_CONF_KERN(io7->pe, port);
243 hose->io_space->start = (unsigned long)IO7_IO_KERN(io7->pe, port);
244 hose->io_space->end = hose->io_space->start + IO7_IO_SPACE - 1;
245 hose->io_space->name = mk_resource_name(io7->pe, port, "IO");
246 hose->io_space->flags = IORESOURCE_IO;
248 hose->mem_space->start = (unsigned long)IO7_MEM_KERN(io7->pe, port);
249 hose->mem_space->end = hose->mem_space->start + IO7_MEM_SPACE - 1;
250 hose->mem_space->name = mk_resource_name(io7->pe, port, "MEM");
251 hose->mem_space->flags = IORESOURCE_MEM;
253 if (request_resource(&ioport_resource, hose->io_space) < 0)
254 printk(KERN_ERR "Failed to request IO on hose %d\n",
256 if (request_resource(&iomem_resource, hose->mem_space) < 0)
257 printk(KERN_ERR "Failed to request MEM on hose %d\n",
261 * Save the existing DMA window settings for later restoration.
263 for (i = 0; i < 4; i++) {
264 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr;
265 io7_port->saved_wmask[i] = csrs->POx_WMASK[i].csr;
266 io7_port->saved_tbase[i] = csrs->POx_TBASE[i].csr;
270 * Set up the PCI to main memory translation windows.
272 * Window 0 is scatter-gather 8MB at 8MB
273 * Window 1 is direct access 1GB at 2GB
274 * Window 2 is scatter-gather (up-to) 1GB at 3GB
275 * Window 3 is disabled
279 * TBIA before modifying windows.
281 marvel_pci_tbi(hose, 0, -1);
284 * Set up window 0 for scatter-gather 8MB at 8MB.
286 hose->sg_isa = iommu_arena_new_node(marvel_cpuid_to_nid(io7->pe),
287 hose, 0x00800000, 0x00800000, 0);
288 hose->sg_isa->align_entry = 8; /* cache line boundary */
289 csrs->POx_WBASE[0].csr =
290 hose->sg_isa->dma_base | wbase_m_ena | wbase_m_sg;
291 csrs->POx_WMASK[0].csr = (hose->sg_isa->size - 1) & wbase_m_addr;
292 csrs->POx_TBASE[0].csr = virt_to_phys(hose->sg_isa->ptes);
295 * Set up window 1 for direct-mapped 1GB at 2GB.
297 csrs->POx_WBASE[1].csr = __direct_map_base | wbase_m_ena;
298 csrs->POx_WMASK[1].csr = (__direct_map_size - 1) & wbase_m_addr;
299 csrs->POx_TBASE[1].csr = 0;
302 * Set up window 2 for scatter-gather (up-to) 1GB at 3GB.
304 hose->sg_pci = iommu_arena_new_node(marvel_cpuid_to_nid(io7->pe),
305 hose, 0xc0000000, 0x40000000, 0);
306 hose->sg_pci->align_entry = 8; /* cache line boundary */
307 csrs->POx_WBASE[2].csr =
308 hose->sg_pci->dma_base | wbase_m_ena | wbase_m_sg;
309 csrs->POx_WMASK[2].csr = (hose->sg_pci->size - 1) & wbase_m_addr;
310 csrs->POx_TBASE[2].csr = virt_to_phys(hose->sg_pci->ptes);
315 csrs->POx_WBASE[3].csr = 0;
318 * Make sure that the AGP Monster Window is disabled.
320 csrs->POx_CTRL.csr &= ~(1UL << 61);
323 printk("FIXME: disabling master aborts\n");
324 csrs->POx_MSK_HEI.csr &= ~(3UL << 14);
327 * TBIA after modifying windows.
329 marvel_pci_tbi(hose, 0, -1);
333 marvel_init_io7(struct io7 *io7)
337 printk("Initializing IO7 at PID %d\n", io7->pe);
340 * Get the Port 7 CSR pointer.
342 io7->csrs = IO7_PORT7_CSRS_KERN(io7->pe);
345 * Init this IO7's hoses.
347 for (i = 0; i < IO7_NUM_PORTS; i++) {
348 io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, i);
349 if (csrs->POx_CACHE_CTL.csr == 8) {
350 io7->ports[i].enabled = 1;
351 io7_init_hose(io7, i);
357 marvel_io7_present(gct6_node *node)
361 if (node->type != GCT_TYPE_HOSE ||
362 node->subtype != GCT_SUBTYPE_IO_PORT_MODULE)
365 pe = (node->id >> 8) & 0xff;
366 printk("Found an IO7 at PID %d\n", pe);
372 marvel_init_vga_hose(void)
374 #ifdef CONFIG_VGA_HOSE
375 u64 *pu64 = (u64 *)((u64)hwrpb + hwrpb->ctbt_offset);
377 if (pu64[7] == 3) { /* TERM_TYPE == graphics */
378 struct pci_controller *hose = NULL;
379 int h = (pu64[30] >> 24) & 0xff; /* TERM_OUT_LOC, hose # */
383 /* FIXME - encoding is going to have to change for Marvel
384 * since hose will be able to overflow a byte...
385 * need to fix this decode when the console
386 * changes its encoding
388 printk("console graphics is on hose %d (console)\n", h);
391 * The console's hose numbering is:
396 * We need to find the hose at that pid and port
400 if ((io7 = marvel_find_io7(pid)))
401 hose = io7->ports[port].hose;
404 printk("Console graphics on hose %d\n", hose->index);
408 #endif /* CONFIG_VGA_HOSE */
411 gct6_search_struct gct_wanted_node_list[] = {
412 { GCT_TYPE_HOSE, GCT_SUBTYPE_IO_PORT_MODULE, marvel_io7_present },
417 * In case the GCT is not complete, let the user specify PIDs with IO7s
418 * at boot time. Syntax is 'io7=a,b,c,...,n' where a-n are the PIDs (decimal)
419 * where IO7s are connected
422 marvel_specify_io7(char *str)
429 pid = simple_strtoul(str, &pchar, 0);
431 printk("User-specified IO7 at PID %lu\n", pid);
432 io7 = alloc_io7(pid);
433 if (io7) marvel_init_io7(io7);
436 if (pchar == str) pchar++;
442 __setup("io7=", marvel_specify_io7);
445 marvel_init_arch(void)
449 /* With multiple PCI busses, we play with I/O as physical addrs. */
450 ioport_resource.end = ~0UL;
451 iomem_resource.end = ~0UL;
453 /* PCI DMA Direct Mapping is 1GB at 2GB. */
454 __direct_map_base = 0x80000000;
455 __direct_map_size = 0x40000000;
457 /* Parse the config tree. */
458 gct6_find_nodes(GCT_NODE_PTR(0), gct_wanted_node_list);
461 for (io7 = NULL; NULL != (io7 = marvel_next_io7(io7)); )
462 marvel_init_io7(io7);
464 /* Check for graphic console location (if any). */
465 marvel_init_vga_hose();
469 marvel_kill_arch(int mode)
475 * PCI Configuration Space access functions
477 * Configuration space addresses have the following format:
479 * |2 2 2 2|1 1 1 1|1 1 1 1|1 1
480 * |3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
481 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
482 * |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|R|R|
483 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
485 * n:24 reserved for hose base
486 * 23:16 bus number (8 bits = 128 possible buses)
487 * 15:11 Device number (5 bits)
488 * 10:8 function number
489 * 7:2 register number
492 * IO7 determines whether to use a type 0 or type 1 config cycle
493 * based on the bus number. Therefore the bus number must be set
494 * to 0 for the root bus on any hose.
496 * The function number selects which function of a multi-function device
497 * (e.g., SCSI and Ethernet).
501 static inline unsigned long
502 build_conf_addr(struct pci_controller *hose, u8 bus,
503 unsigned int devfn, int where)
505 return (hose->config_space_base | (bus << 16) | (devfn << 8) | where);
509 mk_conf_addr(struct pci_dev *dev, int where)
511 struct pci_controller *hose = dev->sysdata;
512 unsigned long addr = 0;
513 struct io7_port *io7_port;
519 /* Check for enabled. */
520 io7_port = hose->sysdata;
521 if (!io7_port->enabled)
524 bus = dev->bus->number;
526 if (hose->first_busno == bus) {
527 /* Don't support idsel > 20 on primary bus. */
528 if (dev->devfn >= PCI_DEVFN(21, 0))
533 addr = build_conf_addr(hose, bus, dev->devfn, where);
535 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
540 marvel_read_config_byte(struct pci_dev *dev, int where, u8 *value)
544 if (0 == (addr = mk_conf_addr(dev, where)))
545 return PCIBIOS_DEVICE_NOT_FOUND;
547 *value = __kernel_ldbu(*(vucp)addr);
548 return PCIBIOS_SUCCESSFUL;
552 marvel_read_config_word(struct pci_dev *dev, int where, u16 *value)
556 if (0 == (addr = mk_conf_addr(dev, where)))
557 return PCIBIOS_DEVICE_NOT_FOUND;
559 *value = __kernel_ldwu(*(vusp)addr);
560 return PCIBIOS_SUCCESSFUL;
564 marvel_read_config_dword(struct pci_dev *dev, int where, u32 *value)
568 if (0 == (addr = mk_conf_addr(dev, where)))
569 return PCIBIOS_DEVICE_NOT_FOUND;
571 *value = *(vuip)addr;
572 return PCIBIOS_SUCCESSFUL;
576 marvel_write_config_byte(struct pci_dev *dev, int where, u8 value)
580 if (0 == (addr = mk_conf_addr(dev, where)))
581 return PCIBIOS_DEVICE_NOT_FOUND;
583 __kernel_stb(value, *(vucp)addr);
585 __kernel_ldbu(*(vucp)addr);
586 return PCIBIOS_SUCCESSFUL;
590 marvel_write_config_word(struct pci_dev *dev, int where, u16 value)
594 if (0 == (addr = mk_conf_addr(dev, where)))
595 return PCIBIOS_DEVICE_NOT_FOUND;
597 __kernel_stw(value, *(vusp)addr);
599 __kernel_ldwu(*(vusp)addr);
600 return PCIBIOS_SUCCESSFUL;
604 marvel_write_config_dword(struct pci_dev *dev, int where, u32 value)
608 if (0 == (addr = mk_conf_addr(dev, where)))
609 return PCIBIOS_DEVICE_NOT_FOUND;
614 return PCIBIOS_SUCCESSFUL;
617 struct pci_ops marvel_pci_ops =
619 read_byte: marvel_read_config_byte,
620 read_word: marvel_read_config_word,
621 read_dword: marvel_read_config_dword,
622 write_byte: marvel_write_config_byte,
623 write_word: marvel_write_config_word,
624 write_dword: marvel_write_config_dword
629 * Other PCI helper functions.
632 marvel_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
634 io7_ioport_csrs *csrs = ((struct io7_port *)hose->sysdata)->csrs;
637 csrs->POx_SG_TBIA.csr = 0;
639 csrs->POx_SG_TBIA.csr;
647 marvel_ioremap(unsigned long addr, unsigned long size)
649 struct pci_controller *hose;
650 unsigned long baddr, last;
651 struct vm_struct *area;
659 #ifdef CONFIG_VGA_HOSE
660 if (pci_vga_hose && __marvel_is_mem_vga(addr)) {
661 addr += pci_vga_hose->mem_space->start;
665 if (!marvel_is_ioaddr(addr))
671 for (hose = hose_head; hose; hose = hose->next) {
672 if ((addr >> 32) == (hose->mem_space->start >> 32))
679 * We have the hose - calculate the bus limits.
681 baddr = addr - hose->mem_space->start;
682 last = baddr + size - 1;
685 * Is it direct-mapped?
687 if ((baddr >= __direct_map_base) &&
688 ((baddr + size - 1) < __direct_map_base + __direct_map_size))
689 return IDENT_ADDR | (baddr - __direct_map_base);
692 * Check the scatter-gather arena.
695 baddr >= (unsigned long)hose->sg_pci->dma_base &&
696 last < (unsigned long)hose->sg_pci->dma_base + hose->sg_pci->size){
699 * Adjust the limits (mappings must be page aligned)
701 baddr -= hose->sg_pci->dma_base;
702 last -= hose->sg_pci->dma_base;
704 size = PAGE_ALIGN(last) - baddr;
709 area = get_vm_area(size, VM_IOREMAP);
710 if (!area) return (unsigned long)NULL;
711 ptes = hose->sg_pci->ptes;
712 for (vaddr = (unsigned long)area->addr;
714 baddr += PAGE_SIZE, vaddr += PAGE_SIZE) {
715 pfn = ptes[baddr >> PAGE_SHIFT];
717 printk("ioremap failed... pte not valid...\n");
721 pfn >>= 1; /* make it a true pfn */
723 if (__alpha_remap_area_pages(VMALLOC_VMADDR(vaddr),
726 printk("FAILED to map...\n");
734 vaddr = (unsigned long)area->addr + (addr & ~PAGE_MASK);
740 * Not found - assume legacy ioremap.
746 marvel_iounmap(unsigned long addr)
748 if (((long)addr >> 41) == -2)
749 return; /* kseg map, nothing to do */
751 return vfree((void *)(PAGE_MASK & addr));
758 struct marvel_rtc_access_info {
759 unsigned long function;
765 __marvel_access_rtc(void *info)
767 struct marvel_rtc_access_info *rtc_access = info;
769 register unsigned long __r0 __asm__("$0");
770 register unsigned long __r16 __asm__("$16") = rtc_access->function;
771 register unsigned long __r17 __asm__("$17") = rtc_access->index;
772 register unsigned long __r18 __asm__("$18") = rtc_access->data;
774 __asm__ __volatile__(
775 "call_pal %4 # cserve rtc"
776 : "=r"(__r16), "=r"(__r17), "=r"(__r18), "=r"(__r0)
777 : "i"(PAL_cserve), "0"(__r16), "1"(__r17), "2"(__r18)
778 : "$1", "$22", "$23", "$24", "$25");
780 rtc_access->data = __r0;
784 __marvel_rtc_io(int write, u8 b, unsigned long addr)
786 struct marvel_rtc_access_info rtc_access = {0, };
791 case 0x70: /* RTC_PORT(0) */
792 if (write) index = b;
796 case 0x71: /* RTC_PORT(1) */
797 rtc_access.index = index;
798 rtc_access.data = BCD_TO_BIN(b);
799 rtc_access.function = 0x49; /* GET_TOY */
800 if (write) rtc_access.function = 0x48; /* PUT_TOY */
803 if (smp_processor_id() != boot_cpuid)
804 smp_call_function_on_cpu(__marvel_access_rtc,
810 __marvel_access_rtc(&rtc_access);
812 __marvel_access_rtc(&rtc_access);
814 ret = BIN_TO_BCD(rtc_access.data);
819 printk(KERN_WARNING "Illegal RTC port %lx\n", addr);
831 * FIXME - for now each cpu is a node by itself
832 * -- no real support for striped mode
836 marvel_pa_to_nid(unsigned long pa)
840 if ((pa >> 43) & 1) /* I/O */
841 cpuid = (~(pa >> 35) & 0xff);
843 cpuid = ((pa >> 34) & 0x3) | ((pa >> (37 - 2)) & (0x1f << 2));
845 return marvel_cpuid_to_nid(cpuid);
849 marvel_cpuid_to_nid(int cpuid)
855 marvel_node_mem_start(int nid)
859 pa = (nid & 0x3) | ((nid & (0x1f << 2)) << 1);
866 marvel_node_mem_size(int nid)
868 return 16UL * 1024 * 1024 * 1024; /* 16GB */
875 #include <linux/agp_backend.h>
876 #include <asm/agp_backend.h>
877 #include <linux/slab.h>
878 #include <linux/delay.h>
880 struct marvel_agp_aperture {
881 struct pci_iommu_arena *arena;
887 marvel_agp_setup(alpha_agp_info *agp)
889 struct marvel_agp_aperture *aper;
891 if (!alpha_agpgart_size)
894 aper = kmalloc(sizeof(*aper), GFP_KERNEL);
895 if (aper == NULL) return -ENOMEM;
897 aper->arena = agp->hose->sg_pci;
898 aper->pg_count = alpha_agpgart_size / PAGE_SIZE;
899 aper->pg_start = iommu_reserve(aper->arena, aper->pg_count,
902 if (aper->pg_start < 0) {
903 printk(KERN_ERR "Failed to reserve AGP memory\n");
908 agp->aperture.bus_base =
909 aper->arena->dma_base + aper->pg_start * PAGE_SIZE;
910 agp->aperture.size = aper->pg_count * PAGE_SIZE;
911 agp->aperture.sysdata = aper;
917 marvel_agp_cleanup(alpha_agp_info *agp)
919 struct marvel_agp_aperture *aper = agp->aperture.sysdata;
922 status = iommu_release(aper->arena, aper->pg_start, aper->pg_count);
923 if (status == -EBUSY) {
925 "Attempted to release bound AGP memory - unbinding\n");
926 iommu_unbind(aper->arena, aper->pg_start, aper->pg_count);
927 status = iommu_release(aper->arena, aper->pg_start,
931 printk(KERN_ERR "Failed to release AGP memory\n");
938 marvel_agp_configure(alpha_agp_info *agp)
940 io7_ioport_csrs *csrs = ((struct io7_port *)agp->hose->sysdata)->csrs;
941 struct io7 *io7 = ((struct io7_port *)agp->hose->sysdata)->io7;
942 unsigned int new_rate = 0;
943 unsigned long agp_pll;
946 * Check the requested mode against the PLL setting.
947 * The agpgart_be code has not programmed the card yet,
948 * so we can still tweak mode here.
950 agp_pll = io7->csrs->POx_RST[IO7_AGP_PORT].csr;
951 switch(IO7_PLL_RNGB(agp_pll)) {
952 case 0x4: /* 2x only */
954 * The PLL is only programmed for 2x, so adjust the
955 * rate to 2x, if necessary.
957 if (agp->mode.bits.rate != 2)
961 case 0x6: /* 1x / 4x */
963 * The PLL is programmed for 1x or 4x. Don't go faster
964 * than requested, so if the requested rate is 2x, use 1x.
966 if (agp->mode.bits.rate == 2)
970 default: /* ??????? */
972 * Don't know what this PLL setting is, take the requested
973 * rate, but warn the user.
975 printk("%s: unknown PLL setting RNGB=%lx (PLL6_CTL=%016lx)\n",
976 __FUNCTION__, IO7_PLL_RNGB(agp_pll), agp_pll);
981 * Set the new rate, if necessary.
984 printk("Requested AGP Rate %dX not compatible "
985 "with PLL setting - using %dX\n",
989 agp->mode.bits.rate = new_rate;
992 printk("Enabling AGP on hose %d: %dX%s RQ %d\n",
993 agp->hose->index, agp->mode.bits.rate,
994 agp->mode.bits.sba ? " - SBA" : "", agp->mode.bits.rq);
996 csrs->AGP_CMD.csr = agp->mode.lw;
1002 marvel_agp_bind_memory(alpha_agp_info *agp, off_t pg_start, agp_memory *mem)
1004 struct marvel_agp_aperture *aper = agp->aperture.sysdata;
1005 return iommu_bind(aper->arena, aper->pg_start + pg_start,
1006 mem->page_count, mem->memory);
1010 marvel_agp_unbind_memory(alpha_agp_info *agp, off_t pg_start, agp_memory *mem)
1012 struct marvel_agp_aperture *aper = agp->aperture.sysdata;
1013 return iommu_unbind(aper->arena, aper->pg_start + pg_start,
1017 static unsigned long
1018 marvel_agp_translate(alpha_agp_info *agp, dma_addr_t addr)
1020 struct marvel_agp_aperture *aper = agp->aperture.sysdata;
1021 unsigned long baddr = addr - aper->arena->dma_base;
1024 if (addr < agp->aperture.bus_base ||
1025 addr >= agp->aperture.bus_base + agp->aperture.size) {
1026 printk("%s: addr out of range\n", __FUNCTION__);
1030 pte = aper->arena->ptes[baddr >> PAGE_SHIFT];
1032 printk("%s: pte not valid\n", __FUNCTION__);
1035 return (pte >> 1) << PAGE_SHIFT;
1038 struct alpha_agp_ops marvel_agp_ops =
1040 setup: marvel_agp_setup,
1041 cleanup: marvel_agp_cleanup,
1042 configure: marvel_agp_configure,
1043 bind: marvel_agp_bind_memory,
1044 unbind: marvel_agp_unbind_memory,
1045 translate: marvel_agp_translate
1049 marvel_agp_info(void)
1051 struct pci_controller *hose;
1052 io7_ioport_csrs *csrs;
1053 alpha_agp_info *agp;
1057 * Find the first IO7 with an AGP card.
1059 * FIXME -- there should be a better way (we want to be able to
1060 * specify and what if the agp card is not video???)
1063 for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; ) {
1064 struct pci_controller *h;
1067 if (!io7->ports[IO7_AGP_PORT].enabled)
1070 h = io7->ports[IO7_AGP_PORT].hose;
1071 addr = (vuip)build_conf_addr(h, 0, PCI_DEVFN(5, 0), 0);
1073 if (*addr != 0xffffffffu) {
1079 printk("MARVEL - using hose %d as AGP\n", hose->index);
1081 if (!hose || !hose->sg_pci)
1085 * Get the csrs from the hose.
1087 csrs = ((struct io7_port *)hose->sysdata)->csrs;
1090 * Allocate the info structure.
1092 agp = kmalloc(sizeof(*agp), GFP_KERNEL);
1097 agp->type = 0 /* FIXME: ALPHA_CORE_AGP */;
1099 agp->private = NULL;
1100 agp->ops = &marvel_agp_ops;
1103 * Aperture - not configured until ops.setup().
1105 agp->aperture.bus_base = 0;
1106 agp->aperture.size = 0;
1107 agp->aperture.sysdata = NULL;
1112 * NOTE: IO7 reports through AGP_STAT that it can support a read queue
1113 * depth of 17 (rq = 0x10). It actually only supports a depth of
1116 agp->capability.lw = csrs->AGP_STAT.csr;
1117 agp->capability.bits.rq = 0xf;
1122 agp->mode.lw = csrs->AGP_CMD.csr;