2 * linux/arch/alpha/kernel/pci.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
9 /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * PCI-PCI bridges cleanup
16 #include <linux/string.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/kernel.h>
21 #include <linux/bootmem.h>
22 #include <asm/machvec.h>
29 * Some string constants used by the various core logics.
32 const char *const pci_io_names[] = {
33 "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
34 "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
37 const char *const pci_mem_names[] = {
38 "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
39 "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
42 const char pci_hae0_name[] = "HAE0";
44 /* Indicate whether we respect the PCI setup left by console. */
45 int __initdata pci_probe_only;
48 * The PCI controller list.
51 struct pci_controller *hose_head, **hose_tail = &hose_head;
52 struct pci_controller *pci_isa_hose;
59 quirk_eisa_bridge(struct pci_dev *dev)
61 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
65 quirk_isa_bridge(struct pci_dev *dev)
67 dev->class = PCI_CLASS_BRIDGE_ISA << 8;
71 quirk_cypress(struct pci_dev *dev)
73 /* The Notorious Cy82C693 chip. */
75 /* The Cypress IDE controller doesn't support native mode, but it
76 has programmable addresses of IDE command/control registers.
77 This violates PCI specifications, confuses the IDE subsystem and
78 causes resource conflicts between the primary HD_CMD register and
79 the floppy controller. Ugh. Fix that. */
80 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
81 dev->resource[0].flags = 0;
82 dev->resource[1].flags = 0;
85 /* The Cypress bridge responds on the PCI bus in the address range
86 0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
87 way to turn this off. The bridge also supports several extended
88 BIOS ranges (disabled after power-up), and some consoles do turn
89 them on. So if we use a large direct-map window, or a large SG
90 window, we must avoid entire 0xfff00000-0xffffffff region. */
91 else if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
92 if (__direct_map_base + __direct_map_size >= 0xfff00000)
93 __direct_map_size = 0xfff00000 - __direct_map_base;
95 struct pci_controller *hose = dev->sysdata;
96 struct pci_iommu_arena *pci = hose->sg_pci;
97 if (pci && pci->dma_base + pci->size >= 0xfff00000)
98 pci->size = 0xfff00000 - pci->dma_base;
103 struct pci_fixup pcibios_fixups[] __initdata = {
104 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375,
106 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378,
108 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693,
113 #define MAX(val1, val2) ((val1) > (val2) ? (val1) : (val2))
114 #define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
120 pcibios_align_resource(void *data, struct resource *res,
121 unsigned long size, unsigned long align)
123 struct pci_dev *dev = data;
124 struct pci_controller *hose = dev->sysdata;
125 unsigned long alignto;
126 unsigned long start = res->start;
128 if (res->flags & IORESOURCE_IO) {
129 /* Make sure we start at our min on all hoses */
130 if (start - hose->io_space->start < PCIBIOS_MIN_IO)
131 start = PCIBIOS_MIN_IO + hose->io_space->start;
134 * Put everything into 0x00-0xff region modulo 0x400
137 start = (start + 0x3ff) & ~0x3ff;
139 else if (res->flags & IORESOURCE_MEM) {
140 /* Make sure we start at our min on all hoses */
141 if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
142 start = PCIBIOS_MIN_MEM + hose->mem_space->start;
145 * The following holds at least for the Low Cost
146 * Alpha implementation of the PCI interface:
148 * In sparse memory address space, the first
149 * octant (16MB) of every 128MB segment is
150 * aliased to the very first 16 MB of the
151 * address space (i.e., it aliases the ISA
152 * memory address space). Thus, we try to
153 * avoid allocating PCI devices in that range.
154 * Can be allocated in 2nd-7th octant only.
155 * Devices that need more than 112MB of
156 * address space must be accessed through
157 * dense memory space only!
160 /* Align to multiple of size of minimum base. */
161 alignto = MAX(0x1000, align);
162 start = ALIGN(start, alignto);
163 if (hose->sparse_mem_base && size <= 7 * 16*MB) {
164 if (((start / (16*MB)) & 0x7) == 0) {
165 start &= ~(128*MB - 1);
167 start = ALIGN(start, alignto);
169 if (start/(128*MB) != (start + size - 1)/(128*MB)) {
170 start &= ~(128*MB - 1);
171 start += (128 + 16)*MB;
172 start = ALIGN(start, alignto);
188 if (!alpha_mv.init_pci)
194 pcibios_setup(char *str)
200 pcibios_fixup_resource(struct resource *res, struct resource *root)
202 res->start += root->start;
203 res->end += root->start;
207 pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
209 /* Update device resources. */
210 struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
213 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
214 if (!dev->resource[i].start)
216 if (dev->resource[i].flags & IORESOURCE_IO)
217 pcibios_fixup_resource(&dev->resource[i],
219 else if (dev->resource[i].flags & IORESOURCE_MEM)
220 pcibios_fixup_resource(&dev->resource[i],
226 pcibios_fixup_bus(struct pci_bus *bus)
228 /* Propogate hose info into the subordinate devices. */
230 struct pci_controller *hose = bus->sysdata;
231 struct list_head *ln;
232 struct pci_dev *dev = bus->self;
237 u32 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
240 bus->resource[0] = hose->io_space;
241 bus->resource[1] = hose->mem_space;
243 /* Adjust hose mem_space limit to prevent PCI allocations
244 in the iommu windows. */
245 pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
246 end = hose->mem_space->start + pci_mem_end;
247 if (hose->mem_space->end > end)
248 hose->mem_space->end = end;
249 } else if (pci_probe_only &&
250 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
251 pci_read_bridge_bases(bus);
252 pcibios_fixup_device_resources(dev, bus);
255 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
256 struct pci_dev *dev = pci_dev_b(ln);
257 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
258 pcibios_fixup_device_resources(dev, bus);
263 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
264 struct resource *res, int resource)
266 struct pci_controller *hose = dev->sysdata;
270 if (resource < PCI_ROM_RESOURCE)
271 where = PCI_BASE_ADDRESS_0 + (resource * 4);
272 else if (resource == PCI_ROM_RESOURCE)
273 where = dev->rom_base_reg;
275 return; /* Don't update non-standard resources here. */
278 /* Point root at the hose root. */
279 if (res->flags & IORESOURCE_IO)
280 root = hose->io_space;
281 if (res->flags & IORESOURCE_MEM)
282 root = hose->mem_space;
284 reg = (res->start - root->start) | (res->flags & 0xf);
285 pci_write_config_dword(dev, where, reg);
286 if ((res->flags & (PCI_BASE_ADDRESS_SPACE
287 | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
288 == (PCI_BASE_ADDRESS_SPACE_MEMORY
289 | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
290 pci_write_config_dword(dev, where+4, 0);
291 printk(KERN_WARNING "PCI: dev %s type 64-bit\n", dev->name);
294 /* ??? FIXME -- record old value for shutdown. */
298 pcibios_update_irq(struct pci_dev *dev, int irq)
300 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
302 /* ??? FIXME -- record old value for shutdown. */
305 /* Most Alphas have straight-forward swizzling needs. */
308 common_swizzle(struct pci_dev *dev, u8 *pinp)
310 struct pci_controller *hose = dev->sysdata;
312 if (dev->bus->number != hose->first_busno) {
315 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
316 /* Move up the chain of bridges. */
317 dev = dev->bus->self;
318 } while (dev->bus->self);
321 /* The slot is the slot of the last bridge. */
324 return PCI_SLOT(dev->devfn);
328 pcibios_fixup_pbus_ranges(struct pci_bus * bus,
329 struct pbus_set_ranges_data * ranges)
331 struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
333 ranges->io_start -= hose->io_space->start;
334 ranges->io_end -= hose->io_space->start;
335 ranges->mem_start -= hose->mem_space->start;
336 ranges->mem_end -= hose->mem_space->start;
337 /* FIXME: On older alphas we could use dense memory space
338 to access prefetchable resources. */
339 ranges->prefetch_start -= hose->mem_space->start;
340 ranges->prefetch_end -= hose->mem_space->start;
344 pcibios_enable_device(struct pci_dev *dev, int mask)
346 /* Nothing to do, since we enable all devices at startup. */
351 * If we set up a device for bus mastering, we need to check the latency
352 * timer as certain firmware forgets to set it properly, as seen
353 * on SX164 and LX164 with SRM.
356 pcibios_set_master(struct pci_dev *dev)
359 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
360 if (lat >= 16) return;
361 printk("PCI: Setting latency timer of device %s to 64\n",
363 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
367 pcibios_claim_console_setup(void)
369 struct list_head *lb;
371 for(lb = pci_root_buses.next; lb != &pci_root_buses; lb = lb->next) {
372 struct pci_bus *b = pci_bus_b(lb);
373 struct list_head *ld;
375 for (ld = b->devices.next; ld != &b->devices; ld = ld->next) {
376 struct pci_dev *dev = pci_dev_b(ld);
379 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
380 struct resource *r = &dev->resource[i];
382 if (r->parent || !r->start || !r->flags)
384 pci_claim_resource(dev, i);
391 common_init_pci(void)
393 struct pci_controller *hose;
397 /* Scan all of the recorded PCI controllers. */
398 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
399 hose->first_busno = next_busno;
400 hose->last_busno = 0xff;
401 bus = pci_scan_bus(next_busno, alpha_mv.pci_ops, hose);
403 next_busno = hose->last_busno = bus->subordinate;
408 pcibios_claim_console_setup();
409 else /* FIXME: `else' will be removed when
410 pci_assign_unassigned_resources() is able to work
411 correctly with [partially] allocated PCI tree. */
412 pci_assign_unassigned_resources();
413 pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
417 struct pci_controller * __init
418 alloc_pci_controller(void)
420 struct pci_controller *hose;
422 hose = alloc_bootmem(sizeof(*hose));
425 hose_tail = &hose->next;
430 struct resource * __init
433 struct resource *res;
435 res = alloc_bootmem(sizeof(*res));
441 /* Provide information on locations of various I/O regions in physical
442 memory. Do this on a per-card basis so that we choose the right hose. */
445 sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
447 struct pci_controller *hose;
450 /* from hose or from bus.devfn */
451 if (which & IOBASE_FROM_HOSE) {
452 for(hose = hose_head; hose; hose = hose->next)
453 if (hose->index == bus) break;
454 if (!hose) return -ENODEV;
456 /* Special hook for ISA access. */
457 if (bus == 0 && dfn == 0) {
460 dev = pci_find_slot(bus, dfn);
467 switch (which & ~IOBASE_FROM_HOSE) {
470 case IOBASE_SPARSE_MEM:
471 return hose->sparse_mem_base;
472 case IOBASE_DENSE_MEM:
473 return hose->dense_mem_base;
474 case IOBASE_SPARSE_IO:
475 return hose->sparse_io_base;
476 case IOBASE_DENSE_IO:
477 return hose->dense_io_base;
478 case IOBASE_ROOT_BUS:
479 return hose->bus->number;
485 /* Return the index of the PCI controller for device PDEV. */
487 pci_controller_num(struct pci_dev *pdev)
489 struct pci_controller *hose = pdev->sysdata;
490 return (hose ? hose->index : -ENXIO);