2 * linux/arch/alpha/kernel/sys_titan.c
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996, 1999 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
7 * Copyright (C) 1999, 2000 Jeff Wiedemeier
9 * Code supporting TITAN systems (EV6+TITAN), currently:
15 #include <linux/config.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
19 #include <linux/sched.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
23 #include <asm/ptrace.h>
24 #include <asm/system.h>
27 #include <asm/bitops.h>
28 #include <asm/mmu_context.h>
30 #include <asm/pgtable.h>
31 #include <asm/core_titan.h>
32 #include <asm/hwrpb.h>
37 #include "machvec_impl.h"
46 * Titan supports up to 4 CPUs
48 static unsigned long titan_cpu_irq_affinity[4] = { ~0UL, ~0UL, ~0UL, ~0UL };
51 * Mask is set (1) if enabled
53 static unsigned long titan_cached_irq_mask;
56 * Need SMP-safe access to interrupt CSRs
58 spinlock_t titan_irq_lock = SPIN_LOCK_UNLOCKED;
61 titan_update_irq_hw(unsigned long mask)
63 register titan_cchip *cchip = TITAN_cchip;
64 unsigned long isa_enable = 1UL << 55;
65 register int bcpu = boot_cpuid;
68 register unsigned long cpm = cpu_present_mask;
69 volatile unsigned long *dim0, *dim1, *dim2, *dim3;
70 unsigned long mask0, mask1, mask2, mask3, dummy;
73 mask0 = mask & titan_cpu_irq_affinity[0];
74 mask1 = mask & titan_cpu_irq_affinity[1];
75 mask2 = mask & titan_cpu_irq_affinity[2];
76 mask3 = mask & titan_cpu_irq_affinity[3];
78 if (bcpu == 0) mask0 |= isa_enable;
79 else if (bcpu == 1) mask1 |= isa_enable;
80 else if (bcpu == 2) mask2 |= isa_enable;
81 else mask3 |= isa_enable;
83 dim0 = &cchip->dim0.csr;
84 dim1 = &cchip->dim1.csr;
85 dim2 = &cchip->dim2.csr;
86 dim3 = &cchip->dim3.csr;
87 if ((cpm & 1) == 0) dim0 = &dummy;
88 if ((cpm & 2) == 0) dim1 = &dummy;
89 if ((cpm & 4) == 0) dim2 = &dummy;
90 if ((cpm & 8) == 0) dim3 = &dummy;
102 volatile unsigned long *dimB;
103 dimB = &cchip->dim0.csr;
104 if (bcpu == 1) dimB = &cchip->dim1.csr;
105 else if (bcpu == 2) dimB = &cchip->dim2.csr;
106 else if (bcpu == 3) dimB = &cchip->dim3.csr;
108 *dimB = mask | isa_enable;
115 titan_enable_irq(unsigned int irq)
117 spin_lock(&titan_irq_lock);
118 titan_cached_irq_mask |= 1UL << (irq - 16);
119 titan_update_irq_hw(titan_cached_irq_mask);
120 spin_unlock(&titan_irq_lock);
124 titan_disable_irq(unsigned int irq)
126 spin_lock(&titan_irq_lock);
127 titan_cached_irq_mask &= ~(1UL << (irq - 16));
128 titan_update_irq_hw(titan_cached_irq_mask);
129 spin_unlock(&titan_irq_lock);
133 titan_startup_irq(unsigned int irq)
135 titan_enable_irq(irq);
136 return 0; /* never anything pending */
140 titan_end_irq(unsigned int irq)
142 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
143 titan_enable_irq(irq);
147 titan_cpu_set_irq_affinity(unsigned int irq, unsigned long affinity)
151 for (cpu = 0; cpu < 4; cpu++) {
152 if (affinity & (1UL << cpu))
153 titan_cpu_irq_affinity[cpu] |= 1UL << irq;
155 titan_cpu_irq_affinity[cpu] &= ~(1UL << irq);
161 titan_set_irq_affinity(unsigned int irq, unsigned long affinity)
163 spin_lock(&titan_irq_lock);
164 titan_cpu_set_irq_affinity(irq - 16, affinity);
165 titan_update_irq_hw(titan_cached_irq_mask);
166 spin_unlock(&titan_irq_lock);
170 titan_device_interrupt(unsigned long vector, struct pt_regs * regs)
172 printk("titan_device_interrupt: NOT IMPLEMENTED YET!! \n");
176 titan_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
180 irq = (vector - 0x800) >> 4;
181 handle_irq(irq, regs);
186 init_titan_irqs(struct hw_interrupt_type * ops, int imin, int imax)
189 for (i = imin; i <= imax; ++i) {
190 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
191 irq_desc[i].handler = ops;
195 static struct hw_interrupt_type titan_irq_type = {
197 startup: titan_startup_irq,
198 shutdown: titan_disable_irq,
199 enable: titan_enable_irq,
200 disable: titan_disable_irq,
201 ack: titan_disable_irq,
203 set_affinity: titan_set_irq_affinity,
207 titan_intr_nop(int irq, void *dev_id, struct pt_regs *regs)
210 * This is a NOP interrupt handler for the purposes of
211 * event counting -- just return.
218 if (alpha_using_srm && !alpha_mv.device_interrupt)
219 alpha_mv.device_interrupt = titan_srm_device_interrupt;
220 if (!alpha_mv.device_interrupt)
221 alpha_mv.device_interrupt = titan_device_interrupt;
223 titan_update_irq_hw(0);
225 init_titan_irqs(&titan_irq_type, 16, 63 + 16);
229 titan_legacy_init_irq(void)
231 /* init the legacy dma controller */
232 outb(0, DMA1_RESET_REG);
233 outb(0, DMA2_RESET_REG);
234 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
235 outb(0, DMA2_MASK_REG);
237 /* init the legacy irq controller */
240 /* init the titan irqs */
245 titan_dispatch_irqs(u64 mask, struct pt_regs *regs)
247 unsigned long vector;
250 * Mask down to those interrupts which are enable on this processor
252 mask &= titan_cpu_irq_affinity[smp_processor_id()];
255 * Dispatch all requested interrupts
258 /* convert to SRM vector... priority is <63> -> <0> */
259 __asm__("ctlz %1, %0" : "=r"(vector) : "r"(mask));
260 vector = 63 - vector;
261 mask &= ~(1UL << vector); /* clear it out */
262 vector = 0x900 + (vector << 4); /* convert to SRM vector */
265 alpha_mv.device_interrupt(vector, regs);
274 titan_late_init(void)
277 * Enable the system error interrupts. These interrupts are
278 * all reported to the kernel as machine checks, so the handler
279 * is a nop so it can be called to count the individual events.
281 request_irq(63+16, titan_intr_nop, SA_INTERRUPT,
282 "CChip Error", NULL);
283 request_irq(62+16, titan_intr_nop, SA_INTERRUPT,
284 "PChip 0 H_Error", NULL);
285 request_irq(61+16, titan_intr_nop, SA_INTERRUPT,
286 "PChip 1 H_Error", NULL);
287 request_irq(60+16, titan_intr_nop, SA_INTERRUPT,
288 "PChip 0 C_Error", NULL);
289 request_irq(59+16, titan_intr_nop, SA_INTERRUPT,
290 "PChip 1 C_Error", NULL);
293 * Register our error handlers.
295 titan_register_error_handlers();
298 * Check if the console left us any error logs.
300 cdl_check_console_data_log();
305 titan_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
310 /* Get the current intline. */
311 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
314 /* Is it explicitly routed through ISA? */
315 if ((irq & 0xF0) == 0xE0)
318 /* Offset by 16 to make room for ISA interrupts 0 - 15. */
326 * This isn't really the right place, but there's some init
327 * that needs to be done after everything is basically up.
334 #ifdef CONFIG_VGA_HOSE
335 locate_and_init_vga(NULL);
344 privateer_init_pci(void)
347 * Hook a couple of extra err interrupts that the
348 * common titan code won't.
350 request_irq(53+16, titan_intr_nop, SA_INTERRUPT,
352 request_irq(50+16, titan_intr_nop, SA_INTERRUPT,
353 "Temperature Warning", NULL);
356 * Finish with the common version.
358 return titan_init_pci();
363 * The System Vectors.
365 struct alpha_machine_vector titan_mv __initmv = {
366 vector_name: "TITAN",
371 machine_check: titan_machine_check,
372 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
373 min_io_address: DEFAULT_IO_BASE,
374 min_mem_address: DEFAULT_MEM_BASE,
375 pci_dac_offset: TITAN_DAC_OFFSET,
377 nr_irqs: 80, /* 64 + 16 */
378 /* device_interrupt will be filled in by titan_init_irq */
380 agp_info: titan_agp_info,
382 init_arch: titan_init_arch,
383 init_irq: titan_legacy_init_irq,
384 init_rtc: common_init_rtc,
385 init_pci: titan_init_pci,
387 kill_arch: titan_kill_arch,
388 pci_map_irq: titan_map_irq,
389 pci_swizzle: common_swizzle,
393 struct alpha_machine_vector privateer_mv __initmv = {
394 vector_name: "PRIVATEER",
399 machine_check: privateer_machine_check,
400 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
401 min_io_address: DEFAULT_IO_BASE,
402 min_mem_address: DEFAULT_MEM_BASE,
403 pci_dac_offset: TITAN_DAC_OFFSET,
405 nr_irqs: 80, /* 64 + 16 */
406 /* device_interrupt will be filled in by titan_init_irq */
408 agp_info: titan_agp_info,
410 init_arch: titan_init_arch,
411 init_irq: titan_legacy_init_irq,
412 init_rtc: common_init_rtc,
413 init_pci: privateer_init_pci,
415 kill_arch: titan_kill_arch,
416 pci_map_irq: titan_map_irq,
417 pci_swizzle: common_swizzle,
419 /* No alpha_mv alias for privateer since we compile it
420 in unconditionally with titan; setup_arch knows how to cope. */