1 #include <linux/module.h>
2 #include <linux/types.h>
3 #include <linux/kernel.h>
4 #include <linux/sched.h>
6 #include <asm/uaccess.h>
9 #include <math-emu/soft-fp.h>
10 #include <math-emu/single.h>
11 #include <math-emu/double.h>
29 #define FOP_FNC_ADDx 0
30 #define FOP_FNC_CVTQL 0
31 #define FOP_FNC_SUBx 1
32 #define FOP_FNC_MULx 2
33 #define FOP_FNC_DIVx 3
34 #define FOP_FNC_CMPxUN 4
35 #define FOP_FNC_CMPxEQ 5
36 #define FOP_FNC_CMPxLT 6
37 #define FOP_FNC_CMPxLE 7
38 #define FOP_FNC_SQRTx 11
39 #define FOP_FNC_CVTxS 12
40 #define FOP_FNC_CVTxT 14
41 #define FOP_FNC_CVTxQ 15
43 #define MISC_TRAPB 0x0000
44 #define MISC_EXCB 0x0400
46 extern unsigned long alpha_read_fp_reg (unsigned long reg);
47 extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
48 extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
49 extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
54 MODULE_DESCRIPTION("FP Software completion module");
56 extern long (*alpha_fp_emul_imprecise)(struct pt_regs *, unsigned long);
57 extern long (*alpha_fp_emul) (unsigned long pc);
59 static long (*save_emul_imprecise)(struct pt_regs *, unsigned long);
60 static long (*save_emul) (unsigned long pc);
62 long do_alpha_fp_emul_imprecise(struct pt_regs *, unsigned long);
63 long do_alpha_fp_emul(unsigned long);
67 save_emul_imprecise = alpha_fp_emul_imprecise;
68 save_emul = alpha_fp_emul;
69 alpha_fp_emul_imprecise = do_alpha_fp_emul_imprecise;
70 alpha_fp_emul = do_alpha_fp_emul;
74 void cleanup_module(void)
76 alpha_fp_emul_imprecise = save_emul_imprecise;
77 alpha_fp_emul = save_emul;
80 #undef alpha_fp_emul_imprecise
81 #define alpha_fp_emul_imprecise do_alpha_fp_emul_imprecise
83 #define alpha_fp_emul do_alpha_fp_emul
89 * Emulate the floating point instruction at address PC. Returns 0 if
90 * emulation fails. Notice that the kernel does not and cannot use FP
91 * regs. This is good because it means that instead of
92 * saving/restoring all fp regs, we simply stick the result of the
93 * operation into the appropriate register.
96 alpha_fp_emul (unsigned long pc)
99 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
100 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
102 unsigned long fa, fb, fc, func, mode, src;
103 unsigned long res, va, vb, vc, swcr, fpcr;
108 get_user(insn, (__u32*)pc);
109 fc = (insn >> 0) & 0x1f; /* destination register */
110 fb = (insn >> 16) & 0x1f;
111 fa = (insn >> 21) & 0x1f;
112 func = (insn >> 5) & 0xf;
113 src = (insn >> 9) & 0x3;
114 mode = (insn >> 11) & 0x3;
117 swcr = swcr_update_status(current->thread.flags, fpcr);
120 /* Dynamic -- get rounding mode from fpcr. */
121 mode = (fpcr >> FPCR_DYN_SHIFT) & 3;
126 va = alpha_read_fp_reg_s(fa);
127 vb = alpha_read_fp_reg_s(fb);
129 FP_UNPACK_SP(SA, &va);
130 FP_UNPACK_SP(SB, &vb);
134 FP_SUB_S(SR, SA, SB);
138 FP_ADD_S(SR, SA, SB);
142 FP_MUL_S(SR, SA, SB);
146 FP_DIV_S(SR, SA, SB);
156 va = alpha_read_fp_reg(fa);
157 vb = alpha_read_fp_reg(fb);
159 if ((func & ~3) == FOP_FNC_CMPxUN) {
160 FP_UNPACK_RAW_DP(DA, &va);
161 FP_UNPACK_RAW_DP(DB, &vb);
162 if (!DA_e && !_FP_FRAC_ZEROP_1(DA)) {
163 FP_SET_EXCEPTION(FP_EX_DENORM);
165 _FP_FRAC_SET_1(DA, _FP_ZEROFRAC_1);
167 if (!DB_e && !_FP_FRAC_ZEROP_1(DB)) {
168 FP_SET_EXCEPTION(FP_EX_DENORM);
170 _FP_FRAC_SET_1(DB, _FP_ZEROFRAC_1);
172 FP_CMP_D(res, DA, DB, 3);
173 vc = 0x4000000000000000;
174 /* CMPTEQ, CMPTUN don't trap on QNaN,
175 while CMPTLT and CMPTLE do */
179 || FP_ISSIGNAN_D(DB))) {
180 FP_SET_EXCEPTION(FP_EX_INVALID);
183 case FOP_FNC_CMPxUN: if (res != 3) vc = 0; break;
184 case FOP_FNC_CMPxEQ: if (res) vc = 0; break;
185 case FOP_FNC_CMPxLT: if (res != -1) vc = 0; break;
186 case FOP_FNC_CMPxLE: if ((long)res > 0) vc = 0; break;
191 FP_UNPACK_DP(DA, &va);
192 FP_UNPACK_DP(DB, &vb);
196 FP_SUB_D(DR, DA, DB);
200 FP_ADD_D(DR, DA, DB);
204 FP_MUL_D(DR, DA, DB);
208 FP_DIV_D(DR, DA, DB);
216 /* It is irritating that DEC encoded CVTST with
217 SRC == T_floating. It is also interesting that
218 the bit used to tell the two apart is /U... */
220 FP_CONV(S,D,1,1,SR,DB);
223 vb = alpha_read_fp_reg_s(fb);
224 FP_UNPACK_SP(SB, &vb);
228 DR_f = SB_f << (52 - 23);
233 if (DB_c == FP_CLS_NAN
234 && (_FP_FRAC_HIGH_RAW_D(DB) & _FP_QNANBIT_D)) {
235 /* AAHB Table B-2 says QNaN should not trigger INV */
238 FP_TO_INT_ROUND_D(vc, DB, 64, 2);
244 vb = alpha_read_fp_reg(fb);
248 /* Notice: We can get here only due to an integer
249 overflow. Such overflows are reported as invalid
250 ops. We return the result the hw would have
252 vc = ((vb & 0xc0000000) << 32 | /* sign and msb */
253 (vb & 0x3fffffff) << 29); /* rest of the int */
254 FP_SET_EXCEPTION (FP_EX_INVALID);
258 FP_FROM_INT_S(SR, (*(long*)&vb), 64, long);
262 FP_FROM_INT_D(DR, (*(long*)&vb), 64, long);
271 if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ))
273 alpha_write_fp_reg_s(fc, vc);
278 if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ))
281 alpha_write_fp_reg(fc, vc);
285 * Take the appropriate action for each possible
286 * floating-point result:
288 * - Set the appropriate bits in the FPCR
289 * - If the specified exception is enabled in the FPCR,
290 * return. The caller (entArith) will dispatch
291 * the appropriate signal to the translated program.
293 * In addition, properly track the exception state in software
294 * as described in the Alpha Architectre Handbook section 4.7.7.3.
298 /* Record exceptions in software control word. */
299 swcr |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT);
300 current->thread.flags |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT);
302 /* Update hardware control register. */
303 fpcr &= (~FPCR_MASK | FPCR_DYN_MASK);
304 fpcr |= ieee_swcr_to_fpcr(swcr);
307 /* Do we generate a signal? */
308 if (_fex & swcr & IEEE_TRAP_ENABLE_MASK) {
314 /* We used to write the destination register here, but DEC FORTRAN
315 requires that the result *always* be written... so we do the write
316 immediately after the operations above. */
322 printk(KERN_ERR "alpha_fp_emul: Invalid FP insn %#x at %#lx\n",
329 alpha_fp_emul_imprecise (struct pt_regs *regs, unsigned long write_mask)
331 unsigned long trigger_pc = regs->pc - 4;
332 unsigned long insn, opcode, rc, no_signal = 0;
337 * Turn off the bits corresponding to registers that are the
338 * target of instructions that set bits in the exception
339 * summary register. We have some slack doing this because a
340 * register that is the target of a trapping instruction can
341 * be written at most once in the trap shadow.
343 * Branches, jumps, TRAPBs, EXCBs and calls to PALcode all
344 * bound the trap shadow, so we need not look any further than
345 * up to the first occurrence of such an instruction.
348 get_user(insn, (__u32*)(trigger_pc));
355 case 0x30 ... 0x3f: /* branches */
359 switch (insn & 0xffff) {
373 write_mask &= ~(1UL << rc);
380 write_mask &= ~(1UL << (rc + 32));
384 /* Re-execute insns in the trap-shadow. */
385 regs->pc = trigger_pc + 4;
386 no_signal = alpha_fp_emul(trigger_pc);