arch/arm/lib/io-readsw-armv4.S

   1 /*
   2  *  linux/arch/arm/lib/io-readsw-armv4.S
   3  *
   4  *  Copyright (C) 1995-2000 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/linkage.h>
  11 #include <asm/assembler.h>
  12 #include <asm/hardware.h>
  13
  14 .insw_bad_alignment:
  15                 adr     r0, .insw_bad_align_msg
  16                 mov     r2, lr
  17                 b       SYMBOL_NAME(panic)
  18 .insw_bad_align_msg:
  19                 .asciz  "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
  20                 .align
  21
  22 .insw_align:    tst     r1, #1
  23                 bne     .insw_bad_alignment
  24
  25                 ldrh    r3, [r0]
  26                 strh    r3, [r1], #2
  27
  28                 subs    r2, r2, #1
  29                 RETINSTR(moveq, pc, lr)
  30
  31 ENTRY(__raw_readsw)
  32                 teq     r2, #0          @ do we have to check for the zero len?
  33                 moveq   pc, lr
  34                 tst     r1, #3
  35                 bne     .insw_align
  36
  37                 stmfd   sp!, {r4, r5, lr}
  38
  39                 subs    r2, r2, #8
  40                 bmi     .no_insw_8
  41
  42 .insw_8_lp:     ldrh    r3, [r0]
  43                 ldrh    r4, [r0]
  44                 orr     r3, r3, r4, lsl #16
  45
  46                 ldrh    r4, [r0]
  47                 ldrh    r5, [r0]
  48                 orr     r4, r4, r5, lsl #16
  49
  50                 ldrh    r5, [r0]
  51                 ldrh    ip, [r0]
  52                 orr     r5, r5, ip, lsl #16
  53
  54                 ldrh    ip, [r0]
  55                 ldrh    lr, [r0]
  56                 orr     ip, ip, lr, lsl #16
  57
  58                 stmia   r1!, {r3 - r5, ip}
  59
  60                 subs    r2, r2, #8
  61                 bpl     .insw_8_lp
  62
  63                 tst     r2, #7
  64                 LOADREGS(eqfd, sp!, {r4, r5, pc})
  65
  66 .no_insw_8:     tst     r2, #4
  67                 beq     .no_insw_4
  68
  69                 ldrh    r3, [r0]
  70                 ldrh    r4, [r0]
  71                 orr     r3, r3, r4, lsl #16
  72
  73                 ldrh    r4, [r0]
  74                 ldrh    ip, [r0]
  75                 orr     r4, r4, ip, lsl #16
  76
  77                 stmia   r1!, {r3, r4}
  78
  79 .no_insw_4:     tst     r2, #2
  80                 beq     .no_insw_2
  81
  82                 ldrh    r3, [r0]
  83                 ldrh    ip, [r0]
  84                 orr     r3, r3, ip, lsl #16
  85
  86                 str     r3, [r1], #4
  87
  88 .no_insw_2:     tst     r2, #1
  89                 ldrneh  r3, [r0]
  90                 strneh  r3, [r1]
  91
  92                 LOADREGS(fd, sp!, {r4, r5, pc})