arch/arm/mach-clps711x/irq.c

   1 /*
   2  *  linux/arch/arm/mach-clps711x/irq.c
   3  *
   4  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/init.h>
  21
  22 #include <asm/mach/irq.h>
  23 #include <asm/hardware.h>
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26
  27 #include <asm/hardware/clps7111.h>
  28
  29 static void mask_irq_int1(unsigned int irq)
  30 {
  31         u32 intmr1;
  32
  33         intmr1 = clps_readl(INTMR1);
  34         intmr1 &= ~(1 << irq);
  35         clps_writel(intmr1, INTMR1);
  36 }
  37
  38 static void mask_ack_irq_int1(unsigned int irq)
  39 {
  40         u32 intmr1;
  41
  42         intmr1 = clps_readl(INTMR1);
  43         intmr1 &= ~(1 << irq);
  44         clps_writel(intmr1, INTMR1);
  45
  46         switch (irq) {
  47         case IRQ_CSINT:  clps_writel(0, COEOI);  break;
  48         case IRQ_TC1OI:  clps_writel(0, TC1EOI); break;
  49         case IRQ_TC2OI:  clps_writel(0, TC2EOI); break;
  50         case IRQ_RTCMI:  clps_writel(0, RTCEOI); break;
  51         case IRQ_TINT:   clps_writel(0, TEOI);   break;
  52         case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
  53         }
  54 }
  55
  56 static void unmask_irq_int1(unsigned int irq)
  57 {
  58         u32 intmr1;
  59
  60         intmr1 = clps_readl(INTMR1);
  61         intmr1 |= 1 << irq;
  62         clps_writel(intmr1, INTMR1);
  63 }
  64
  65 static void mask_irq_int2(unsigned int irq)
  66 {
  67         u32 intmr2;
  68
  69         intmr2 = clps_readl(INTMR2);
  70         intmr2 &= ~(1 << (irq - 16));
  71         clps_writel(intmr2, INTMR2);
  72 }
  73
  74 static void mask_ack_irq_int2(unsigned int irq)
  75 {
  76         u32 intmr2;
  77
  78         intmr2 = clps_readl(INTMR2);
  79         intmr2 &= ~(1 << (irq - 16));
  80         clps_writel(intmr2, INTMR2);
  81
  82         switch (irq) {
  83         case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
  84         }
  85 }
  86
  87 static void unmask_irq_int2(unsigned int irq)
  88 {
  89         u32 intmr2;
  90
  91         intmr2 = clps_readl(INTMR2);
  92         intmr2 |= 1 << (irq - 16);
  93         clps_writel(intmr2, INTMR2);
  94 }
  95
  96 void __init clps711x_init_irq(void)
  97 {
  98         unsigned int i;
  99
 100         for (i = 0; i < NR_IRQS; i++) {
 101                 if (INT1_IRQS & (1 << i)) {
 102                         irq_desc[i].valid       = 1;
 103                         irq_desc[i].probe_ok    = 1;
 104                         irq_desc[i].mask_ack    = (INT1_ACK_IRQS & (1 << i)) ?
 105                                                    mask_ack_irq_int1 :
 106                                                    mask_irq_int1;
 107                         irq_desc[i].mask        = mask_irq_int1;
 108                         irq_desc[i].unmask      = unmask_irq_int1;
 109                 }
 110                 if (INT2_IRQS & (1 << i)) {
 111                         irq_desc[i].valid       = 1;
 112                         irq_desc[i].probe_ok    = 1;
 113                         irq_desc[i].mask_ack    = (INT2_ACK_IRQS & (1 << i)) ?
 114                                                    mask_ack_irq_int2 :
 115                                                    mask_irq_int2;
 116                         irq_desc[i].mask        = mask_irq_int2;
 117                         irq_desc[i].unmask      = unmask_irq_int2;
 118                 }
 119         }
 120
 121         /*
 122          * Disable interrupts
 123          */
 124         clps_writel(0, INTMR1);
 125         clps_writel(0, INTMR2);
 126
 127         /*
 128          * Clear down any pending interrupts
 129          */
 130         clps_writel(0, COEOI);
 131         clps_writel(0, TC1EOI);
 132         clps_writel(0, TC2EOI);
 133         clps_writel(0, RTCEOI);
 134         clps_writel(0, TEOI);
 135         clps_writel(0, UMSEOI);
 136         clps_writel(0, SYNCIO);
 137         clps_writel(0, KBDEOI);
 138 }