arch/arm/mach-clps711x/irq.c

   1 /*
   2  *  linux/arch/arm/mach-clps711x/irq.c
   3  *
   4  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/kernel.h>
  23 #include <linux/timer.h>
  24
  25 #include <asm/mach/irq.h>
  26 #include <asm/hardware.h>
  27 #include <asm/io.h>
  28 #include <asm/irq.h>
  29
  30 #include <asm/hardware/clps7111.h>
  31
  32 static void mask_irq_int1(unsigned int irq)
  33 {
  34         u32 intmr1;
  35
  36         intmr1 = clps_readl(INTMR1);
  37         intmr1 &= ~(1 << irq);
  38         clps_writel(intmr1, INTMR1);
  39 }
  40
  41 static void mask_ack_irq_int1(unsigned int irq)
  42 {
  43         u32 intmr1;
  44
  45         intmr1 = clps_readl(INTMR1);
  46         intmr1 &= ~(1 << irq);
  47         clps_writel(intmr1, INTMR1);
  48
  49         switch (irq) {
  50         case IRQ_CSINT:  clps_writel(0, COEOI);  break;
  51         case IRQ_TC1OI:  clps_writel(0, TC1EOI); break;
  52         case IRQ_TC2OI:  clps_writel(0, TC2EOI); break;
  53         case IRQ_RTCMI:  clps_writel(0, RTCEOI); break;
  54         case IRQ_TINT:   clps_writel(0, TEOI);   break;
  55         case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
  56         }
  57 }
  58
  59 static void unmask_irq_int1(unsigned int irq)
  60 {
  61         u32 intmr1;
  62
  63         intmr1 = clps_readl(INTMR1);
  64         intmr1 |= 1 << irq;
  65         clps_writel(intmr1, INTMR1);
  66 }
  67
  68 static void mask_irq_int2(unsigned int irq)
  69 {
  70         u32 intmr2;
  71
  72         intmr2 = clps_readl(INTMR2);
  73         intmr2 &= ~(1 << (irq - 16));
  74         clps_writel(intmr2, INTMR2);
  75 }
  76
  77 static void mask_ack_irq_int2(unsigned int irq)
  78 {
  79         u32 intmr2;
  80
  81         intmr2 = clps_readl(INTMR2);
  82         intmr2 &= ~(1 << (irq - 16));
  83         clps_writel(intmr2, INTMR2);
  84
  85         switch (irq) {
  86         case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
  87         }
  88 }
  89
  90 static void unmask_irq_int2(unsigned int irq)
  91 {
  92         u32 intmr2;
  93
  94         intmr2 = clps_readl(INTMR2);
  95         intmr2 |= 1 << (irq - 16);
  96         clps_writel(intmr2, INTMR2);
  97 }
  98
  99 void __init clps711x_init_irq(void)
 100 {
 101         unsigned int i;
 102
 103         for (i = 0; i < NR_IRQS; i++) {
 104                 if (INT1_IRQS & (1 << i)) {
 105                         irq_desc[i].valid       = 1;
 106                         irq_desc[i].probe_ok    = 1;
 107                         irq_desc[i].mask_ack    = (INT1_ACK_IRQS & (1 << i)) ?
 108                                                    mask_ack_irq_int1 :
 109                                                    mask_irq_int1;
 110                         irq_desc[i].mask        = mask_irq_int1;
 111                         irq_desc[i].unmask      = unmask_irq_int1;
 112                 }
 113                 if (INT2_IRQS & (1 << i)) {
 114                         irq_desc[i].valid       = 1;
 115                         irq_desc[i].probe_ok    = 1;
 116                         irq_desc[i].mask_ack    = (INT2_ACK_IRQS & (1 << i)) ?
 117                                                    mask_ack_irq_int2 :
 118                                                    mask_irq_int2;
 119                         irq_desc[i].mask        = mask_irq_int2;
 120                         irq_desc[i].unmask      = unmask_irq_int2;
 121                 }
 122         }
 123
 124         /*
 125          * Disable interrupts
 126          */
 127         clps_writel(0, INTMR1);
 128         clps_writel(0, INTMR2);
 129
 130         /*
 131          * Clear down any pending interrupts
 132          */
 133         clps_writel(0, COEOI);
 134         clps_writel(0, TC1EOI);
 135         clps_writel(0, TC2EOI);
 136         clps_writel(0, RTCEOI);
 137         clps_writel(0, TEOI);
 138         clps_writel(0, UMSEOI);
 139         clps_writel(0, SYNCIO);
 140         clps_writel(0, KBDEOI);
 141 }