2 * linux/arch/i386/kernel/head.S -- the 32-bit startup code.
4 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Enhanced CPU detection and feature setting code by Mike Jagdis
7 * and Martin Mares, November 1997.
11 #include <linux/config.h>
12 #include <linux/threads.h>
13 #include <linux/linkage.h>
14 #include <asm/segment.h>
16 #include <asm/pgtable.h>
19 #define OLD_CL_MAGIC_ADDR 0x90020
20 #define OLD_CL_MAGIC 0xA33F
21 #define OLD_CL_BASE_ADDR 0x90000
22 #define OLD_CL_OFFSET 0x90022
23 #define NEW_CL_POINTER 0x228 /* Relative to real mode data */
26 * References to members of the boot_cpu_data structure.
29 #define CPU_PARAMS SYMBOL_NAME(boot_cpu_data)
30 #define X86 CPU_PARAMS+0
31 #define X86_VENDOR CPU_PARAMS+1
32 #define X86_MODEL CPU_PARAMS+2
33 #define X86_MASK CPU_PARAMS+3
34 #define X86_HARD_MATH CPU_PARAMS+6
35 #define X86_CPUID CPU_PARAMS+8
36 #define X86_CAPABILITY CPU_PARAMS+12
37 #define X86_VENDOR_ID CPU_PARAMS+36 /* tied to NCAPINTS in cpufeature.h */
40 * swapper_pg_dir is the main page directory, address 0x00101000
42 * On entry, %esi points to the real-mode code as a 32-bit pointer.
46 * Set segments to known values
49 movl $(__KERNEL_DS),%eax
59 * New page tables may be in 4Mbyte page mode and may
60 * be using the global pages.
62 * NOTE! If we are on a 486 we may have no cr4 at all!
63 * So we do not try to touch it unless we really have
64 * some bits in it to set. This won't work if the BSP
65 * implements cr4 but this AP does not -- very unlikely
66 * but be warned! The same applies to the pse feature
67 * if not equally supported. --macro
69 * NOTE! We have to correct for the fact that we're
70 * not yet offset PAGE_OFFSET..
72 #define cr4_bits mmu_cr4_features-__PAGE_OFFSET
75 movl %cr4,%eax # Turn on paging options (PSE,PAE,..)
82 * Initialize page tables
84 movl $pg0-__PAGE_OFFSET,%edi /* initialize page tables */
85 movl $007,%eax /* "007" doesn't mean with right to kill, but
89 cmp $empty_zero_page-__PAGE_OFFSET,%edi
96 movl $swapper_pg_dir-__PAGE_OFFSET,%eax
97 movl %eax,%cr3 /* set the page table pointer.. */
100 movl %eax,%cr0 /* ..and set paging (PG) bit */
101 jmp 1f /* flush the prefetch-queue */
104 jmp *%eax /* make sure eip is relocated */
106 /* Set up the stack pointer */
111 jz 1f /* Initial CPU cleans BSS */
116 #endif /* CONFIG_SMP */
119 * Clear BSS first so that there are no surprises...
120 * No need to cld as DF is already clear from cld above...
123 movl $ SYMBOL_NAME(__bss_start),%edi
124 movl $ SYMBOL_NAME(_end),%ecx
130 * start system 32-bit setup. We need to re-do some of the things done
131 * in 16-bit mode for the "real" operations.
135 * Initialize eflags. Some BIOS's leave bits like NT set. This would
136 * confuse the debugger if this code is traced.
137 * XXX - best to initialize before switching to protected mode.
142 * Copy bootup parameters out of the way. First 2kB of
143 * _empty_zero_page is for boot parameters, second 2kB
144 * is for the command line.
146 * Note: %esi still has the pointer to the real-mode data.
148 movl $ SYMBOL_NAME(empty_zero_page),%edi
157 movl SYMBOL_NAME(empty_zero_page)+NEW_CL_POINTER,%esi
159 jnz 2f # New command line protocol
160 cmpw $(OLD_CL_MAGIC),OLD_CL_MAGIC_ADDR
162 movzwl OLD_CL_OFFSET,%esi
163 addl $(OLD_CL_BASE_ADDR),%esi
165 movl $ SYMBOL_NAME(empty_zero_page)+2048,%edi
172 movl $-1,X86_CPUID # -1 for no CPUID initially
174 /* check if it is 486 or 386. */
176 * XXX - this does a lot of unnecessary setup. Alignment checks don't
177 * apply at our cpl of 0 and the stack ought to be aligned already, and
178 * we don't need to preserve eflags.
181 movb $3,X86 # at least 386
183 popl %eax # get EFLAGS
184 movl %eax,%ecx # save original EFLAGS
185 xorl $0x40000,%eax # flip AC bit in EFLAGS
186 pushl %eax # copy to EFLAGS
188 pushfl # get new EFLAGS
189 popl %eax # put it in eax
190 xorl %ecx,%eax # change in flags
191 andl $0x40000,%eax # check if AC bit changed
194 movb $4,X86 # at least 486
196 xorl $0x200000,%eax # check ID flag
198 popfl # if we are on a straight 486DX, SX, or
199 pushfl # 487SX we can't change it
202 pushl %ecx # restore original EFLAGS
207 /* get vendor info */
208 xorl %eax,%eax # call CPUID with 0 -> return vendor ID
210 movl %eax,X86_CPUID # save CPUID level
211 movl %ebx,X86_VENDOR_ID # lo 4 chars
212 movl %edx,X86_VENDOR_ID+4 # next 4 chars
213 movl %ecx,X86_VENDOR_ID+8 # last 4 chars
215 orl %eax,%eax # do we have processor info as well?
218 movl $1,%eax # Use the CPUID instruction to get CPU type
220 movb %al,%cl # save reg for future use
221 andb $0x0f,%ah # mask processor family
223 andb $0xf0,%al # mask model
226 andb $0x0f,%cl # mask mask revision
228 movl %edx,X86_CAPABILITY
231 movl %cr0,%eax # 486 or better
232 andl $0x80000011,%eax # Save PG,PE,ET
233 orl $0x50022,%eax # set AM, WP, NE and MP
236 is386: pushl %ecx # restore original EFLAGS
239 andl $0x80000011,%eax # Save PG,PE,ET
246 ljmp $(__KERNEL_CS),$1f
247 1: movl $(__KERNEL_DS),%eax # reload all the segment registers
248 movl %eax,%ds # after changing gdt.
253 movl $(__KERNEL_DS), %eax
254 movl %eax,%ss # Reload the stack pointer (segment only)
256 lss stack_start,%esp # Load processor stack
260 cld # gcc2 wants the direction flag cleared at all times
264 je 1f # the first CPU calls start_kernel
265 # all other CPUs call initialize_secondary
266 call SYMBOL_NAME(initialize_secondary)
270 call SYMBOL_NAME(start_kernel)
272 jmp L6 # main should never return here, but
273 # just in case, we know what happens.
278 * We depend on ET to be correct. This checks for 287/387.
281 movb $0,X86_HARD_MATH
287 movl %cr0,%eax /* no coprocessor: have to set bits */
288 xorl $4,%eax /* set EM */
292 1: movb $1,X86_HARD_MATH
293 .byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */
299 * sets up a idt with 256 entries pointing to
300 * ignore_int, interrupt gates. It doesn't actually load
301 * idt - that can be done only after paging has been enabled
302 * and the kernel moved to PAGE_OFFSET. Interrupts
303 * are enabled elsewhere, when we can be relatively
304 * sure everything is ok.
308 movl $(__KERNEL_CS << 16),%eax
309 movw %dx,%ax /* selector = 0x0010 = cs */
310 movw $0x8E00,%dx /* interrupt gate - dpl=0, present */
312 lea SYMBOL_NAME(idt_table),%edi
323 .long SYMBOL_NAME(init_task_union)+8192
326 /* This is the default interrupt "handler" :-) */
328 .asciz "Unknown interrupt, stack: %p %p %p %p\n"
332 movl $(__KERNEL_DS),%eax
340 call SYMBOL_NAME(printk)
345 * The interrupt descriptor table has room for 256 idt's,
346 * the global descriptor table is dependent on the number
347 * of tasks we can have..
349 #define IDT_ENTRIES 256
350 #define GDT_ENTRIES (__TSS(NR_CPUS))
353 .globl SYMBOL_NAME(idt)
354 .globl SYMBOL_NAME(gdt)
359 .word IDT_ENTRIES*8-1 # idt contains 256 entries
361 .long SYMBOL_NAME(idt_table)
365 .word GDT_ENTRIES*8-1
367 .long SYMBOL_NAME(gdt_table)
370 * This is initialized to create an identity-mapping at 0-8M (for bootup
371 * purposes) and another mapping of the 0-8M area at virtual address
375 ENTRY(swapper_pg_dir)
378 .fill BOOT_USER_PGD_PTRS-2,4,0
379 /* default: 766 entries */
382 /* default: 254 entries */
383 .fill BOOT_KERNEL_PGD_PTRS-2,4,0
386 * The page tables are initialized to only 8MB here - the final page
387 * tables are set up later depending on memory size.
396 * empty_zero_page must immediately follow the page tables ! (The
397 * initialization loop counts until empty_zero_page)
401 ENTRY(empty_zero_page)
406 * Real beginning of normal "text" segment
412 * This starts the data section. Note that the above is all
413 * in the text section because it has alignment requirements
414 * that we cannot fulfill any other way.
420 * This contains typically 140 quadwords, depending on NR_CPUS.
422 * NOTE! Make sure the gdt descriptor in head.S matches this if you
426 .quad 0x0000000000000000 /* NULL descriptor */
427 .quad 0x0000000000000000 /* not used */
428 .quad 0x00cf9a000000ffff /* 0x10 kernel 4GB code at 0x00000000 */
429 .quad 0x00cf92000000ffff /* 0x18 kernel 4GB data at 0x00000000 */
430 .quad 0x00cffa000000ffff /* 0x23 user 4GB code at 0x00000000 */
431 .quad 0x00cff2000000ffff /* 0x2b user 4GB data at 0x00000000 */
432 .quad 0x0000000000000000 /* not used */
433 .quad 0x0000000000000000 /* not used */
435 * The APM segments have byte granularity and their bases
436 * and limits are set at run time.
438 .quad 0x0040920000000000 /* 0x40 APM set up for bad BIOS's */
439 .quad 0x00409a0000000000 /* 0x48 APM CS code */
440 .quad 0x00009a0000000000 /* 0x50 APM CS 16 code (16 bit) */
441 .quad 0x0040920000000000 /* 0x58 APM DS data */
442 .fill NR_CPUS*4,8,0 /* space for TSS's and LDT's */