1 #include <linux/config.h>
2 #include <linux/ptrace.h>
3 #include <linux/errno.h>
4 #include <linux/signal.h>
5 #include <linux/sched.h>
6 #include <linux/ioport.h>
7 #include <linux/interrupt.h>
8 #include <linux/timex.h>
9 #include <linux/slab.h>
10 #include <linux/random.h>
11 #include <linux/smp_lock.h>
12 #include <linux/init.h>
13 #include <linux/kernel_stat.h>
15 #include <asm/atomic.h>
16 #include <asm/system.h>
19 #include <asm/bitops.h>
20 #include <asm/pgtable.h>
21 #include <asm/delay.h>
25 #include <linux/irq.h>
28 * Common place to define all x86 IRQ vectors
30 * This builds up the IRQ handler stubs using some ugly macros in irq.h
32 * These macros create the low-level assembly IRQ routines that save
33 * register context and call do_IRQ(). do_IRQ() then does all the
34 * operations that are needed to keep the AT (or SMP IOAPIC)
35 * interrupt-controller happy.
43 #define BUILD_16_IRQS(x) \
44 BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
45 BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
46 BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
47 BI(x,c) BI(x,d) BI(x,e) BI(x,f)
50 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
51 * (these are usually mapped to vectors 0x20-0x2f)
55 #ifdef CONFIG_X86_IO_APIC
57 * The IO-APIC gives us many more interrupt sources. Most of these
58 * are unused but an SMP system is supposed to have enough memory ...
59 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
60 * across the spectrum, so we really want to be prepared to get all
61 * of these. Plus, more powerful systems might have more than 64
64 * (these are usually mapped into the 0x30-0xff vector range)
66 BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
67 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
68 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
69 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd)
77 * The following vectors are part of the Linux architecture, there
78 * is no hardware IRQ pin equivalent for them, they are triggered
79 * through the ICC by us (IPIs)
82 BUILD_SMP_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
83 BUILD_SMP_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
84 BUILD_SMP_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
88 * every pentium local APIC has two 'local interrupts', with a
89 * soft-definable vector attached to both interrupts, one of
90 * which is a timer interrupt, the other one is error counter
91 * overflow. Linux uses the local APIC timer interrupt to get
92 * a much simpler SMP time architecture:
94 #ifdef CONFIG_X86_LOCAL_APIC
95 BUILD_SMP_TIMER_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR)
96 BUILD_SMP_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
97 BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
101 IRQ##x##y##_interrupt
103 #define IRQLIST_16(x) \
104 IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
105 IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
106 IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
107 IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
109 void (*interrupt[NR_IRQS])(void) = {
112 #ifdef CONFIG_X86_IO_APIC
113 IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
114 IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
115 IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
116 IRQLIST_16(0xc), IRQLIST_16(0xd)
124 * This is the 'legacy' 8259A Programmable Interrupt Controller,
125 * present in the majority of PC/AT boxes.
126 * plus some generic x86 specific things if generic specifics makes
128 * this file should become arch/i386/kernel/irq.c when the old irq.c
129 * moves to arch independent land
132 spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
134 static void end_8259A_irq (unsigned int irq)
136 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
137 enable_8259A_irq(irq);
140 #define shutdown_8259A_irq disable_8259A_irq
142 void mask_and_ack_8259A(unsigned int);
144 static unsigned int startup_8259A_irq(unsigned int irq)
146 enable_8259A_irq(irq);
147 return 0; /* never anything pending */
150 static struct hw_interrupt_type i8259A_irq_type = {
162 * 8259A PIC functions to handle ISA devices:
166 * This contains the irq mask for both 8259A irq controllers,
168 static unsigned int cached_irq_mask = 0xffff;
170 #define __byte(x,y) (((unsigned char *)&(y))[x])
171 #define cached_21 (__byte(0,cached_irq_mask))
172 #define cached_A1 (__byte(1,cached_irq_mask))
175 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
176 * boards the timer interrupt is not really connected to any IO-APIC pin,
177 * it's fed to the master 8259A's IR0 line only.
179 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
180 * this 'mixed mode' IRQ handling costs nothing because it's only used
183 unsigned long io_apic_irqs;
185 void disable_8259A_irq(unsigned int irq)
187 unsigned int mask = 1 << irq;
190 spin_lock_irqsave(&i8259A_lock, flags);
191 cached_irq_mask |= mask;
193 outb(cached_A1,0xA1);
195 outb(cached_21,0x21);
196 spin_unlock_irqrestore(&i8259A_lock, flags);
199 void enable_8259A_irq(unsigned int irq)
201 unsigned int mask = ~(1 << irq);
204 spin_lock_irqsave(&i8259A_lock, flags);
205 cached_irq_mask &= mask;
207 outb(cached_A1,0xA1);
209 outb(cached_21,0x21);
210 spin_unlock_irqrestore(&i8259A_lock, flags);
213 int i8259A_irq_pending(unsigned int irq)
215 unsigned int mask = 1<<irq;
219 spin_lock_irqsave(&i8259A_lock, flags);
221 ret = inb(0x20) & mask;
223 ret = inb(0xA0) & (mask >> 8);
224 spin_unlock_irqrestore(&i8259A_lock, flags);
229 void make_8259A_irq(unsigned int irq)
231 disable_irq_nosync(irq);
232 io_apic_irqs &= ~(1<<irq);
233 irq_desc[irq].handler = &i8259A_irq_type;
238 * This function assumes to be called rarely. Switching between
239 * 8259A registers is slow.
240 * This has to be protected by the irq controller spinlock
241 * before being called.
243 static inline int i8259A_irq_real(unsigned int irq)
246 int irqmask = 1<<irq;
249 outb(0x0B,0x20); /* ISR register */
250 value = inb(0x20) & irqmask;
251 outb(0x0A,0x20); /* back to the IRR register */
254 outb(0x0B,0xA0); /* ISR register */
255 value = inb(0xA0) & (irqmask >> 8);
256 outb(0x0A,0xA0); /* back to the IRR register */
261 * Careful! The 8259A is a fragile beast, it pretty
262 * much _has_ to be done exactly like this (mask it
263 * first, _then_ send the EOI, and the order of EOI
264 * to the two 8259s is important!
266 void mask_and_ack_8259A(unsigned int irq)
268 unsigned int irqmask = 1 << irq;
271 spin_lock_irqsave(&i8259A_lock, flags);
273 * Lightweight spurious IRQ detection. We do not want
274 * to overdo spurious IRQ handling - it's usually a sign
275 * of hardware problems, so we only do the checks we can
276 * do without slowing down good hardware unnecesserily.
278 * Note that IRQ7 and IRQ15 (the two spurious IRQs
279 * usually resulting from the 8259A-1|2 PICs) occur
280 * even if the IRQ is masked in the 8259A. Thus we
281 * can check spurious 8259A IRQs without doing the
282 * quite slow i8259A_irq_real() call for every IRQ.
283 * This does not cover 100% of spurious interrupts,
284 * but should be enough to warn the user that there
285 * is something bad going on ...
287 if (cached_irq_mask & irqmask)
288 goto spurious_8259A_irq;
289 cached_irq_mask |= irqmask;
293 inb(0xA1); /* DUMMY - (do we need this?) */
294 outb(cached_A1,0xA1);
295 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
296 outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
298 inb(0x21); /* DUMMY - (do we need this?) */
299 outb(cached_21,0x21);
300 outb(0x60+irq,0x20); /* 'Specific EOI' to master */
302 spin_unlock_irqrestore(&i8259A_lock, flags);
307 * this is the slow path - should happen rarely.
309 if (i8259A_irq_real(irq))
311 * oops, the IRQ _is_ in service according to the
312 * 8259A - not spurious, go handle it.
314 goto handle_real_irq;
317 static int spurious_irq_mask;
319 * At this point we can be sure the IRQ is spurious,
320 * lets ACK and report it. [once per IRQ]
322 if (!(spurious_irq_mask & irqmask)) {
323 printk("spurious 8259A interrupt: IRQ%d.\n", irq);
324 spurious_irq_mask |= irqmask;
326 atomic_inc(&irq_err_count);
328 * Theoretically we do not have to handle this IRQ,
329 * but in Linux this does not cause problems and is
332 goto handle_real_irq;
336 void __init init_8259A(int auto_eoi)
340 spin_lock_irqsave(&i8259A_lock, flags);
342 outb(0xff, 0x21); /* mask all of 8259A-1 */
343 outb(0xff, 0xA1); /* mask all of 8259A-2 */
346 * outb_p - this has to work on a wide range of PC hardware.
348 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
349 outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
350 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
352 outb_p(0x03, 0x21); /* master does Auto EOI */
354 outb_p(0x01, 0x21); /* master expects normal EOI */
356 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
357 outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
358 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
359 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
360 is to be investigated) */
364 * in AEOI mode we just have to mask the interrupt
367 i8259A_irq_type.ack = disable_8259A_irq;
369 i8259A_irq_type.ack = mask_and_ack_8259A;
371 udelay(100); /* wait for 8259A to initialize */
373 outb(cached_21, 0x21); /* restore master IRQ mask */
374 outb(cached_A1, 0xA1); /* restore slave IRQ mask */
376 spin_unlock_irqrestore(&i8259A_lock, flags);
380 * Note that on a 486, we don't want to do a SIGFPE on an irq13
381 * as the irq is unreliable, and exception 16 works correctly
382 * (ie as explained in the intel literature). On a 386, you
383 * can't use exception 16 due to bad IBM design, so we have to
384 * rely on the less exact irq13.
386 * Careful.. Not only is IRQ13 unreliable, but it is also
387 * leads to races. IBM designers who came up with it should
391 static void math_error_irq(int cpl, void *dev_id, struct pt_regs *regs)
393 extern void math_error(void *);
395 if (ignore_irq13 || !boot_cpu_data.hard_math)
397 math_error((void *)regs->eip);
401 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
402 * so allow interrupt sharing.
404 static struct irqaction irq13 = { math_error_irq, 0, 0, "fpu", NULL, NULL };
407 * IRQ2 is cascade interrupt to second interrupt controller
411 static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL};
415 void __init init_ISA_irqs (void)
419 #ifdef CONFIG_X86_LOCAL_APIC
424 for (i = 0; i < NR_IRQS; i++) {
425 irq_desc[i].status = IRQ_DISABLED;
426 irq_desc[i].action = 0;
427 irq_desc[i].depth = 1;
431 * 16 old-style INTA-cycle interrupts:
433 irq_desc[i].handler = &i8259A_irq_type;
436 * 'high' PCI IRQs filled in on demand
438 irq_desc[i].handler = &no_irq_type;
443 void __init init_IRQ(void)
447 #ifndef CONFIG_X86_VISWS_APIC
450 init_VISWS_APIC_irqs();
453 * Cover the whole vector space, no vector can escape
454 * us. (some of these will be overridden and become
455 * 'special' SMP interrupts)
457 for (i = 0; i < NR_IRQS; i++) {
458 int vector = FIRST_EXTERNAL_VECTOR + i;
459 if (vector != SYSCALL_VECTOR)
460 set_intr_gate(vector, interrupt[i]);
465 * IRQ0 must be given a fixed assignment and initialized,
466 * because it's used before the IO-APIC is set up.
468 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
471 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
472 * IPI, driven by wakeup.
474 set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
476 /* IPI for invalidation */
477 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
479 /* IPI for generic function call */
480 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
483 #ifdef CONFIG_X86_LOCAL_APIC
484 /* self generated IPI for local APIC timer */
485 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
487 /* IPI vectors for APIC spurious and error interrupts */
488 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
489 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
493 * Set the clock to HZ Hz, we already have a valid
496 outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
497 outb_p(LATCH & 0xff , 0x40); /* LSB */
498 outb(LATCH >> 8 , 0x40); /* MSB */
505 * External FPU? Set up irq13 if so, for
506 * original braindamaged IBM FERR coupling.
508 if (boot_cpu_data.hard_math && !cpu_has_fpu)
509 setup_irq(13, &irq13);