2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIP report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
35 #include <linux/config.h>
36 #include <linux/init.h>
39 #include <linux/kernel_stat.h>
40 #include <linux/smp_lock.h>
41 #include <linux/irq.h>
42 #include <linux/bootmem.h>
44 #include <linux/delay.h>
45 #include <linux/mc146818rtc.h>
47 #include <asm/pgalloc.h>
48 #include <asm/smpboot.h>
50 /* Set if we find a B stepping CPU */
51 static int smp_b_stepping;
53 /* Setup configured maximum number of CPUs to activate */
54 static int max_cpus = -1;
56 /* Total count of live CPUs */
59 /* Number of siblings per CPU package */
60 int smp_num_siblings = 1;
61 int __initdata phys_proc_id[NR_CPUS]; /* Package ID of each logical CPU */
63 /* Bitmask of currently online CPUs */
64 unsigned long cpu_online_map;
66 static volatile unsigned long cpu_callin_map;
67 static volatile unsigned long cpu_callout_map;
69 /* Per CPU bogomips and other parameters */
70 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
72 /* Set when the idlers are all forked */
73 int smp_threads_ready;
76 * Setup routine for controlling SMP activation
78 * Command-line option of "nosmp" or "maxcpus=0" will disable SMP
79 * activation entirely (the MPS table probe still happens, though).
81 * Command-line option of "maxcpus=<NUM>", where <NUM> is an integer
82 * greater than 0, limits the maximum number of CPUs activated in
86 static int __init nosmp(char *str)
92 __setup("nosmp", nosmp);
94 static int __init maxcpus(char *str)
96 get_option(&str, &max_cpus);
100 __setup("maxcpus=", maxcpus);
103 * Trampoline 80x86 program as an array.
106 extern unsigned char trampoline_data [];
107 extern unsigned char trampoline_end [];
108 static unsigned char *trampoline_base;
111 * Currently trivial. Write the real->protected mode
112 * bootstrap into the page concerned. The caller
113 * has made sure it's suitably aligned.
116 static unsigned long __init setup_trampoline(void)
118 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
119 return virt_to_phys(trampoline_base);
123 * We are called very early to get the low memory for the
124 * SMP bootup trampoline page.
126 void __init smp_alloc_memory(void)
128 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
130 * Has to be in very low memory so we can execute
133 if (__pa(trampoline_base) >= 0x9F000)
138 * The bootstrap kernel entry code has set these up. Save them for
142 void __init smp_store_cpu_info(int id)
144 struct cpuinfo_x86 *c = cpu_data + id;
150 c->pgtable_cache_sz = 0;
153 * Mask B, Pentium, but not Pentium MMX
155 if (c->x86_vendor == X86_VENDOR_INTEL &&
157 c->x86_mask >= 1 && c->x86_mask <= 4 &&
160 * Remember we have B step Pentia with bugs
166 * Architecture specific routine called by the kernel just before init is
167 * fired off. This allows the BP to have everything in order [we hope].
168 * At the end of this all the APs will hit the system scheduling and off
169 * we go. Each AP will load the system gdt's and jump through the kernel
170 * init into idle(). At this point the scheduler will one day take over
171 * and give them jobs to do. smp_callin is a standard routine
172 * we use to track CPUs as they power up.
175 static atomic_t smp_commenced = ATOMIC_INIT(0);
177 void __init smp_commence(void)
180 * Lets the callins below out of their loop.
182 Dprintk("Setting commenced=1, go go go\n");
185 atomic_set(&smp_commenced,1);
189 * TSC synchronization.
191 * We first check wether all CPUs have their TSC's synchronized,
192 * then we print a warning if not, and always resync.
195 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
196 static atomic_t tsc_count_start = ATOMIC_INIT(0);
197 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
198 static unsigned long long tsc_values[NR_CPUS];
202 extern unsigned long fast_gettimeoffset_quotient;
205 * accurate 64-bit/32-bit division, expanded to 32-bit divisions and 64-bit
206 * multiplication. Not terribly optimized but we need it at boot time only
210 * == (a1 + a2*(2^32)) / b
211 * == a1/b + a2*(2^32/b)
212 * == a1/b + a2*((2^32-1)/b) + a2/b + (a2*((2^32-1) % b))/b
213 * ^---- (this multiplication can overflow)
216 static unsigned long long __init div64 (unsigned long long a, unsigned long b0)
219 unsigned long long res;
221 a1 = ((unsigned int*)&a)[0];
222 a2 = ((unsigned int*)&a)[1];
225 (unsigned long long)a2 * (unsigned long long)(0xffffffff/b0) +
227 (a2 * (0xffffffff % b0)) / b0;
232 static void __init synchronize_tsc_bp (void)
235 unsigned long long t0;
236 unsigned long long sum, avg;
238 unsigned long one_usec;
241 printk("checking TSC synchronization across CPUs: ");
243 one_usec = ((1<<30)/fast_gettimeoffset_quotient)*(1<<2);
245 atomic_set(&tsc_start_flag, 1);
249 * We loop a few times to get a primed instruction cache,
250 * then the last pass is more or less synchronized and
251 * the BP and APs set their cycle counters to zero all at
252 * once. This reduces the chance of having random offsets
253 * between the processors, and guarantees that the maximum
254 * delay between the cycle counters is never bigger than
255 * the latency of information-passing (cachelines) between
258 for (i = 0; i < NR_LOOPS; i++) {
260 * all APs synchronize but they loop on '== num_cpus'
262 while (atomic_read(&tsc_count_start) != smp_num_cpus-1) mb();
263 atomic_set(&tsc_count_stop, 0);
266 * this lets the APs save their current TSC:
268 atomic_inc(&tsc_count_start);
270 rdtscll(tsc_values[smp_processor_id()]);
272 * We clear the TSC in the last loop:
278 * Wait for all APs to leave the synchronization point:
280 while (atomic_read(&tsc_count_stop) != smp_num_cpus-1) mb();
281 atomic_set(&tsc_count_start, 0);
283 atomic_inc(&tsc_count_stop);
287 for (i = 0; i < smp_num_cpus; i++) {
291 avg = div64(sum, smp_num_cpus);
294 for (i = 0; i < smp_num_cpus; i++) {
295 delta = tsc_values[i] - avg;
299 * We report bigger than 2 microseconds clock differences.
301 if (delta > 2*one_usec) {
307 realdelta = div64(delta, one_usec);
308 if (tsc_values[i] < avg)
309 realdelta = -realdelta;
311 printk("BIOS BUG: CPU#%d improperly initialized, has %ld usecs TSC skew! FIXED.\n",
321 static void __init synchronize_tsc_ap (void)
326 * smp_num_cpus is not necessarily known at the time
327 * this gets called, so we first wait for the BP to
328 * finish SMP initialization:
330 while (!atomic_read(&tsc_start_flag)) mb();
332 for (i = 0; i < NR_LOOPS; i++) {
333 atomic_inc(&tsc_count_start);
334 while (atomic_read(&tsc_count_start) != smp_num_cpus) mb();
336 rdtscll(tsc_values[smp_processor_id()]);
340 atomic_inc(&tsc_count_stop);
341 while (atomic_read(&tsc_count_stop) != smp_num_cpus) mb();
346 extern void calibrate_delay(void);
348 static atomic_t init_deasserted;
350 void __init smp_callin(void)
353 unsigned long timeout;
356 * If waken up by an INIT in an 82489DX configuration
357 * we may get here before an INIT-deassert IPI reaches
358 * our local APIC. We have to wait for the IPI or we'll
359 * lock up on an APIC access.
361 if (!clustered_apic_mode)
362 while (!atomic_read(&init_deasserted));
365 * (This works even if the APIC is not enabled.)
367 phys_id = GET_APIC_ID(apic_read(APIC_ID));
368 cpuid = current->processor;
369 if (test_and_set_bit(cpuid, &cpu_online_map)) {
370 printk("huh, phys CPU#%d, CPU#%d already present??\n",
374 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
377 * STARTUP IPIs are fragile beasts as they might sometimes
378 * trigger some glue motherboard logic. Complete APIC bus
379 * silence for 1 second, this overestimates the time the
380 * boot CPU is spending to send the up to 2 STARTUP IPIs
381 * by a factor of two. This should be enough.
385 * Waiting 2s total for startup (udelay is not yet working)
387 timeout = jiffies + 2*HZ;
388 while (time_before(jiffies, timeout)) {
390 * Has the boot CPU finished it's STARTUP sequence?
392 if (test_bit(cpuid, &cpu_callout_map))
397 if (!time_before(jiffies, timeout)) {
398 printk("BUG: CPU%d started up but did not get a callout!\n",
404 * the boot CPU has finished the init stage and is spinning
405 * on callin_map until we finish. We are free to set up this
406 * CPU, first the APIC. (this is probably redundant on most
410 Dprintk("CALLIN, before setup_local_APIC().\n");
412 * Because we use NMIs rather than the INIT-STARTUP sequence to
413 * bootstrap the CPUs, the APIC may be in a weird state. Kick it.
415 if (clustered_apic_mode)
423 * Must be done before calibration delay is computed
425 mtrr_init_secondary_cpu ();
431 Dprintk("Stack at about %p\n",&cpuid);
434 * Save our processor parameters
436 smp_store_cpu_info(cpuid);
439 * Allow the master to continue.
441 set_bit(cpuid, &cpu_callin_map);
444 * Synchronize the TSC with the BP
447 synchronize_tsc_ap();
452 extern int cpu_idle(void);
455 * Activate a secondary processor.
457 int __init start_secondary(void *unused)
460 * Dont put anything before smp_callin(), SMP
461 * booting is too fragile that we want to limit the
462 * things done here to the most necessary things.
466 while (!atomic_read(&smp_commenced))
469 * low-memory mappings have been cleared, flush them from
470 * the local TLBs too.
478 * Everything has been set up for the secondary
479 * CPUs - they just need to reload everything
480 * from the task structure
481 * This function must not return.
483 void __init initialize_secondary(void)
486 * We don't actually need to load the full TSS,
487 * basically just the stack pointer and the eip.
494 :"r" (current->thread.esp),"r" (current->thread.eip));
502 static int __init fork_by_hand(void)
506 * don't care about the eip and regs settings since
507 * we'll never reschedule the forked task.
509 return do_fork(CLONE_VM|CLONE_PID, 0, ®s, 0);
512 /* which physical APIC ID maps to which logical CPU number */
513 volatile int physical_apicid_2_cpu[MAX_APICID];
514 /* which logical CPU number maps to which physical APIC ID */
515 volatile int cpu_2_physical_apicid[NR_CPUS];
517 /* which logical APIC ID maps to which logical CPU number */
518 volatile int logical_apicid_2_cpu[MAX_APICID];
519 /* which logical CPU number maps to which logical APIC ID */
520 volatile int cpu_2_logical_apicid[NR_CPUS];
522 static inline void init_cpu_to_apicid(void)
523 /* Initialize all maps between cpu number and apicids */
527 for (apicid = 0; apicid < MAX_APICID; apicid++) {
528 physical_apicid_2_cpu[apicid] = BAD_APICID;
529 logical_apicid_2_cpu[apicid] = BAD_APICID;
531 for (cpu = 0; cpu < NR_CPUS; cpu++) {
532 cpu_2_physical_apicid[cpu] = BAD_APICID;
533 cpu_2_logical_apicid[cpu] = BAD_APICID;
537 static inline void map_cpu_to_boot_apicid(int cpu, int apicid)
539 * set up a mapping between cpu and apicid. Uses logical apicids for multiquad,
540 * else physical apic ids
543 if (clustered_apic_mode == CLUSTERED_APIC_NUMAQ) {
544 logical_apicid_2_cpu[apicid] = cpu;
545 cpu_2_logical_apicid[cpu] = apicid;
547 physical_apicid_2_cpu[apicid] = cpu;
548 cpu_2_physical_apicid[cpu] = apicid;
552 static inline void unmap_cpu_to_boot_apicid(int cpu, int apicid)
554 * undo a mapping between cpu and apicid. Uses logical apicids for multiquad,
555 * else physical apic ids
558 if (clustered_apic_mode == CLUSTERED_APIC_NUMAQ) {
559 logical_apicid_2_cpu[apicid] = BAD_APICID;
560 cpu_2_logical_apicid[cpu] = BAD_APICID;
562 physical_apicid_2_cpu[apicid] = BAD_APICID;
563 cpu_2_physical_apicid[cpu] = BAD_APICID;
568 static inline void inquire_remote_apic(int apicid)
570 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
571 char *names[] = { "ID", "VERSION", "SPIV" };
574 printk("Inquiring remote APIC #%d...\n", apicid);
576 for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
577 printk("... APIC #%d %s: ", apicid, names[i]);
582 apic_wait_icr_idle();
584 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
585 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
590 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
591 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
594 case APIC_ICR_RR_VALID:
595 status = apic_read(APIC_RRR);
596 printk("%08x\n", status);
605 static int wakeup_secondary_via_NMI(int logical_apicid)
607 * Poke the other CPU in the eye to wake it up. Remember that the normal
608 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
609 * won't ... remember to clear down the APIC, etc later.
612 unsigned long send_status = 0, accept_status = 0;
616 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
618 /* Boot on the stack */
619 /* Kick the second */
620 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
622 Dprintk("Waiting for send to finish...\n");
627 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
628 } while (send_status && (timeout++ < 1000));
631 * Give the other CPU some time to accept the IPI.
635 * Due to the Pentium erratum 3AP.
637 maxlvt = get_maxlvt();
639 apic_read_around(APIC_SPIV);
640 apic_write(APIC_ESR, 0);
642 accept_status = (apic_read(APIC_ESR) & 0xEF);
643 Dprintk("NMI sent.\n");
646 printk("APIC never delivered???\n");
648 printk("APIC delivery error (%lx).\n", accept_status);
650 return (send_status | accept_status);
653 static int wakeup_secondary_via_INIT(int phys_apicid, unsigned long start_eip)
655 unsigned long send_status = 0, accept_status = 0;
656 int maxlvt, timeout, num_starts, j;
658 Dprintk("Asserting INIT.\n");
661 * Turn INIT on target chip
663 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
668 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
671 Dprintk("Waiting for send to finish...\n");
676 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
677 } while (send_status && (timeout++ < 1000));
681 Dprintk("Deasserting INIT.\n");
684 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
687 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
689 Dprintk("Waiting for send to finish...\n");
694 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
695 } while (send_status && (timeout++ < 1000));
697 atomic_set(&init_deasserted, 1);
700 * Should we send STARTUP IPIs ?
702 * Determine this based on the APIC version.
703 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
705 if (APIC_INTEGRATED(apic_version[phys_apicid]))
711 * Run STARTUP IPI loop.
713 Dprintk("#startup loops: %d.\n", num_starts);
715 maxlvt = get_maxlvt();
717 for (j = 1; j <= num_starts; j++) {
718 Dprintk("Sending STARTUP #%d.\n",j);
719 apic_read_around(APIC_SPIV);
720 apic_write(APIC_ESR, 0);
722 Dprintk("After apic_write.\n");
729 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
731 /* Boot on the stack */
732 /* Kick the second */
733 apic_write_around(APIC_ICR, APIC_DM_STARTUP
734 | (start_eip >> 12));
737 * Give the other CPU some time to accept the IPI.
741 Dprintk("Startup point 1.\n");
743 Dprintk("Waiting for send to finish...\n");
748 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
749 } while (send_status && (timeout++ < 1000));
752 * Give the other CPU some time to accept the IPI.
756 * Due to the Pentium erratum 3AP.
759 apic_read_around(APIC_SPIV);
760 apic_write(APIC_ESR, 0);
762 accept_status = (apic_read(APIC_ESR) & 0xEF);
763 if (send_status || accept_status)
766 Dprintk("After Startup.\n");
769 printk("APIC never delivered???\n");
771 printk("APIC delivery error (%lx).\n", accept_status);
773 return (send_status | accept_status);
776 extern unsigned long cpu_initialized;
778 static void __init do_boot_cpu (int apicid)
780 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
781 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
784 struct task_struct *idle;
785 unsigned long boot_error = 0;
787 unsigned long start_eip;
788 unsigned short nmi_high = 0, nmi_low = 0;
792 * We can't use kernel_thread since we must avoid to
793 * reschedule the child.
795 if (fork_by_hand() < 0)
796 panic("failed fork for CPU %d", cpu);
799 * We remove it from the pidhash and the runqueue
800 * once we got the process:
802 idle = init_task.prev_task;
804 panic("No idle process for CPU %d", cpu);
806 idle->processor = cpu;
807 idle->cpus_runnable = 1 << cpu; /* we schedule the first task manually */
809 map_cpu_to_boot_apicid(cpu, apicid);
811 idle->thread.eip = (unsigned long) start_secondary;
813 del_from_runqueue(idle);
814 unhash_process(idle);
815 init_tasks[cpu] = idle;
817 /* start_eip had better be page-aligned! */
818 start_eip = setup_trampoline();
820 /* So we see what's up */
821 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
822 stack_start.esp = (void *) (1024 + PAGE_SIZE + (char *)idle);
825 * This grunge runs the startup process for
826 * the targeted processor.
829 atomic_set(&init_deasserted, 0);
831 Dprintk("Setting warm reset code and vector.\n");
833 if (clustered_apic_mode == CLUSTERED_APIC_NUMAQ) {
834 /* stash the current NMI vector, so we can put things back */
835 nmi_high = *((volatile unsigned short *) TRAMPOLINE_HIGH);
836 nmi_low = *((volatile unsigned short *) TRAMPOLINE_LOW);
839 CMOS_WRITE(0xa, 0xf);
842 *((volatile unsigned short *) TRAMPOLINE_HIGH) = start_eip >> 4;
844 *((volatile unsigned short *) TRAMPOLINE_LOW) = start_eip & 0xf;
848 * Be paranoid about clearing APIC errors.
850 if (!clustered_apic_mode && APIC_INTEGRATED(apic_version[apicid])) {
851 apic_read_around(APIC_SPIV);
852 apic_write(APIC_ESR, 0);
857 * Status is now clean
862 * Starting actual IPI sequence...
865 if (clustered_apic_mode == CLUSTERED_APIC_NUMAQ)
866 boot_error = wakeup_secondary_via_NMI(apicid);
868 boot_error = wakeup_secondary_via_INIT(apicid, start_eip);
872 * allow APs to start initializing.
874 Dprintk("Before Callout %d.\n", cpu);
875 set_bit(cpu, &cpu_callout_map);
876 Dprintk("After Callout %d.\n", cpu);
879 * Wait 5s total for a response
881 for (timeout = 0; timeout < 50000; timeout++) {
882 if (test_bit(cpu, &cpu_callin_map))
883 break; /* It has booted */
887 if (test_bit(cpu, &cpu_callin_map)) {
888 /* number CPUs logically, starting from 1 (BSP is 0) */
890 printk("CPU%d: ", cpu);
891 print_cpu_info(&cpu_data[cpu]);
892 Dprintk("CPU has booted.\n");
895 if (*((volatile unsigned char *)phys_to_virt(8192))
897 /* trampoline started but...? */
898 printk("Stuck ??\n");
900 /* trampoline code not run */
901 printk("Not responding.\n");
903 if (!clustered_apic_mode)
904 inquire_remote_apic(apicid);
909 /* Try to put things back the way they were before ... */
910 unmap_cpu_to_boot_apicid(cpu, apicid);
911 clear_bit(cpu, &cpu_callout_map); /* was set here (do_boot_cpu()) */
912 clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */
913 clear_bit(cpu, &cpu_online_map); /* was set in smp_callin() */
917 /* mark "stuck" area as not stuck */
918 *((volatile unsigned long *)phys_to_virt(8192)) = 0;
920 if(clustered_apic_mode == CLUSTERED_APIC_NUMAQ) {
921 printk("Restoring NMI vector\n");
922 *((volatile unsigned short *) TRAMPOLINE_HIGH) = nmi_high;
923 *((volatile unsigned short *) TRAMPOLINE_LOW) = nmi_low;
927 cycles_t cacheflush_time;
929 static void smp_tune_scheduling (void)
931 unsigned long cachesize; /* kB */
932 unsigned long bandwidth = 350; /* MB/s */
934 * Rough estimation for SMP scheduling, this is the number of
935 * cycles it takes for a fully memory-limited process to flush
936 * the SMP-local cache.
938 * (For a P5 this pretty much means we will choose another idle
939 * CPU almost always at wakeup time (this is due to the small
940 * L1 cache), on PIIs it's around 50-100 usecs, depending on
946 * this basically disables processor-affinity
947 * scheduling on SMP without a TSC.
952 cachesize = boot_cpu_data.x86_cache_size;
953 if (cachesize == -1) {
954 cachesize = 16; /* Pentiums, 2x8kB cache */
958 cacheflush_time = (cpu_khz>>10) * (cachesize<<10) / bandwidth;
961 printk("per-CPU timeslice cutoff: %ld.%02ld usecs.\n",
962 (long)cacheflush_time/(cpu_khz/1000),
963 ((long)cacheflush_time*100/(cpu_khz/1000)) % 100);
967 * Cycle through the processors sending APIC IPIs to boot each.
970 extern int prof_multiplier[NR_CPUS];
971 extern int prof_old_multiplier[NR_CPUS];
972 extern int prof_counter[NR_CPUS];
974 static int boot_cpu_logical_apicid;
975 /* Where the IO area was mapped on multiquad, always 0 otherwise */
978 int cpu_sibling_map[NR_CPUS] __cacheline_aligned;
980 void __init smp_boot_cpus(void)
982 int apicid, cpu, bit;
984 if ((clustered_apic_mode == CLUSTERED_APIC_NUMAQ) && (numnodes > 1)) {
985 printk("Remapping cross-quad port I/O for %d quads\n",
987 printk("xquad_portio vaddr 0x%08lx, len %08lx\n",
988 (u_long) xquad_portio,
989 (u_long) numnodes * XQUAD_PORTIO_LEN);
990 xquad_portio = ioremap (XQUAD_PORTIO_BASE,
991 numnodes * XQUAD_PORTIO_LEN);
995 /* Must be done before other processors booted */
996 mtrr_init_boot_cpu ();
999 * Initialize the logical to physical CPU number mapping
1000 * and the per-CPU profiling counter/multiplier
1003 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1004 prof_counter[cpu] = 1;
1005 prof_old_multiplier[cpu] = 1;
1006 prof_multiplier[cpu] = 1;
1009 init_cpu_to_apicid();
1012 * Setup boot CPU information
1014 smp_store_cpu_info(0); /* Final full version of the data */
1015 printk("CPU%d: ", 0);
1016 print_cpu_info(&cpu_data[0]);
1019 * We have the boot CPU online for sure.
1021 set_bit(0, &cpu_online_map);
1022 if (clustered_apic_mode == CLUSTERED_APIC_XAPIC)
1023 boot_cpu_logical_apicid = physical_to_logical_apicid(boot_cpu_physical_apicid);
1025 boot_cpu_logical_apicid = logical_smp_processor_id();
1026 map_cpu_to_boot_apicid(0, boot_cpu_apicid);
1028 global_irq_holder = 0;
1029 current->processor = 0;
1031 smp_tune_scheduling();
1034 * If we couldnt find an SMP configuration at boot time,
1035 * get out of here now!
1037 if (!smp_found_config) {
1038 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1039 #ifndef CONFIG_VISWS
1042 cpu_online_map = phys_cpu_present_map = 1;
1044 if (APIC_init_uniprocessor())
1045 printk(KERN_NOTICE "Local APIC not detected."
1046 " Using dummy APIC emulation.\n");
1051 * Should not be necessary because the MP table should list the boot
1052 * CPU too, but we do it for the sake of robustness anyway.
1053 * Makes no sense to do this check in clustered apic mode, so skip it
1055 if (!clustered_apic_mode &&
1056 !test_bit(boot_cpu_physical_apicid, &phys_cpu_present_map)) {
1057 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1058 boot_cpu_physical_apicid);
1059 phys_cpu_present_map |= (1 << hard_smp_processor_id());
1063 * If we couldn't find a local APIC, then get out of here now!
1065 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1066 !test_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability)) {
1067 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1068 boot_cpu_physical_apicid);
1069 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1070 #ifndef CONFIG_VISWS
1073 cpu_online_map = phys_cpu_present_map = 1;
1078 verify_local_APIC();
1081 * If SMP should be disabled, then really disable it!
1084 smp_found_config = 0;
1085 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1086 #ifndef CONFIG_VISWS
1089 cpu_online_map = phys_cpu_present_map = 1;
1097 if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_physical_apicid)
1101 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1103 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1104 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1105 * clustered apic ID.
1107 Dprintk("CPU present map: %lx\n", phys_cpu_present_map);
1109 for (bit = 0; bit < NR_CPUS; bit++) {
1110 apicid = cpu_present_to_apicid(bit);
1112 * Don't even attempt to start the boot CPU!
1114 if (apicid == boot_cpu_apicid)
1117 if (!(phys_cpu_present_map & (1ul << bit)))
1119 if ((max_cpus >= 0) && (max_cpus <= cpucount+1))
1122 do_boot_cpu(apicid);
1125 * Make sure we unmap all failed CPUs
1127 if ((boot_apicid_to_cpu(apicid) == -1) &&
1128 (phys_cpu_present_map & (1ul << bit)))
1129 printk("CPU #%d/0x%02x not responding - cannot use it.\n",
1134 * Cleanup possible dangling ends...
1136 #ifndef CONFIG_VISWS
1139 * Install writable page 0 entry to set BIOS data area.
1144 * Paranoid: Set warm reset code and vector here back
1145 * to default values.
1149 *((volatile long *) phys_to_virt(0x467)) = 0;
1154 * Allow the user to impress friends.
1157 Dprintk("Before bogomips.\n");
1159 printk(KERN_ERR "Error: only one processor found.\n");
1161 unsigned long bogosum = 0;
1162 for (cpu = 0; cpu < NR_CPUS; cpu++)
1163 if (cpu_online_map & (1<<cpu))
1164 bogosum += cpu_data[cpu].loops_per_jiffy;
1165 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1167 bogosum/(500000/HZ),
1168 (bogosum/(5000/HZ))%100);
1169 Dprintk("Before bogocount - setting activated=1.\n");
1171 smp_num_cpus = cpucount + 1;
1174 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1175 Dprintk("Boot done.\n");
1178 * If Hyper-Threading is avaialble, construct cpu_sibling_map[], so
1179 * that we can tell the sibling CPU efficiently.
1181 if (test_bit(X86_FEATURE_HT, boot_cpu_data.x86_capability)
1182 && smp_num_siblings > 1) {
1183 for (cpu = 0; cpu < NR_CPUS; cpu++)
1184 cpu_sibling_map[cpu] = NO_PROC_ID;
1186 for (cpu = 0; cpu < smp_num_cpus; cpu++) {
1189 for (i = 0; i < smp_num_cpus; i++) {
1192 if (phys_proc_id[cpu] == phys_proc_id[i]) {
1193 cpu_sibling_map[cpu] = i;
1194 printk("cpu_sibling_map[%d] = %d\n", cpu, cpu_sibling_map[cpu]);
1198 if (cpu_sibling_map[cpu] == NO_PROC_ID) {
1199 smp_num_siblings = 1;
1200 printk(KERN_WARNING "WARNING: No sibling found for CPU %d.\n", cpu);
1205 #ifndef CONFIG_VISWS
1207 * Here we can be sure that there is an IO-APIC in the system. Let's
1210 if (!skip_ioapic_setup && nr_ioapics)
1215 * Set up all local APIC timers in the system:
1217 setup_APIC_clocks();
1220 * Synchronize the TSC with the AP
1222 if (cpu_has_tsc && cpucount)
1223 synchronize_tsc_bp();