2 * pci.c - Low-Level PCI Access in IA-64
4 * Derived from bios32.c of i386 tree.
5 * Copyright (C) 2002, 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Bjorn Helgaas <bjorn_helgaas@hp.com>
9 * Note: Above list of copyright holders is incomplete...
11 #include <linux/config.h>
13 #include <linux/acpi.h>
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/ioport.h>
19 #include <linux/slab.h>
20 #include <linux/smp_lock.h>
21 #include <linux/spinlock.h>
23 #include <asm/machvec.h>
26 #include <asm/segment.h>
27 #include <asm/system.h>
43 #define DBG(x...) printk(x)
48 struct pci_fixup pcibios_fixups[1];
50 struct pci_ops *pci_root_ops;
52 int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value);
53 int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value);
57 * Low-level SAL-based PCI configuration access functions. Note that SAL
58 * calls are already serialized (via sal_lock), so we don't need another
59 * synchronization mechanism here.
62 #define PCI_SAL_ADDRESS(seg, bus, dev, fn, reg) \
63 ((u64)(seg << 24) | (u64)(bus << 16) | \
64 (u64)(dev << 11) | (u64)(fn << 8) | (u64)(reg))
67 pci_sal_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
72 if (!value || (seg > 255) || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255))
75 result = ia64_sal_pci_config_read(PCI_SAL_ADDRESS(seg, bus, dev, fn, reg), len, &data);
83 pci_sal_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
85 if ((seg > 255) || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255))
88 return ia64_sal_pci_config_write(PCI_SAL_ADDRESS(seg, bus, dev, fn, reg), len, value);
93 pci_sal_read_config_byte (struct pci_dev *dev, int where, u8 *value)
101 result = pci_sal_read(PCI_SEGMENT(dev), dev->bus->number, PCI_SLOT(dev->devfn),
102 PCI_FUNC(dev->devfn), where, 1, &data);
110 pci_sal_read_config_word (struct pci_dev *dev, int where, u16 *value)
118 result = pci_sal_read(PCI_SEGMENT(dev), dev->bus->number, PCI_SLOT(dev->devfn),
119 PCI_FUNC(dev->devfn), where, 2, &data);
127 pci_sal_read_config_dword (struct pci_dev *dev, int where, u32 *value)
132 return pci_sal_read(PCI_SEGMENT(dev), dev->bus->number, PCI_SLOT(dev->devfn),
133 PCI_FUNC(dev->devfn), where, 4, value);
137 pci_sal_write_config_byte (struct pci_dev *dev, int where, u8 value)
139 return pci_sal_write(PCI_SEGMENT(dev), dev->bus->number, PCI_SLOT(dev->devfn),
140 PCI_FUNC(dev->devfn), where, 1, value);
144 pci_sal_write_config_word (struct pci_dev *dev, int where, u16 value)
146 return pci_sal_write(PCI_SEGMENT(dev), dev->bus->number, PCI_SLOT(dev->devfn),
147 PCI_FUNC(dev->devfn), where, 2, value);
151 pci_sal_write_config_dword (struct pci_dev *dev, int where, u32 value)
153 return pci_sal_write(PCI_SEGMENT(dev), dev->bus->number, PCI_SLOT(dev->devfn),
154 PCI_FUNC(dev->devfn), where, 4, value);
157 struct pci_ops pci_sal_ops = {
158 pci_sal_read_config_byte,
159 pci_sal_read_config_word,
160 pci_sal_read_config_dword,
161 pci_sal_write_config_byte,
162 pci_sal_write_config_word,
163 pci_sal_write_config_dword
168 * Initialization. Uses the SAL interface
171 static struct pci_controller *
172 alloc_pci_controller (int seg)
174 struct pci_controller *controller;
176 controller = kmalloc(sizeof(*controller), GFP_KERNEL);
180 memset(controller, 0, sizeof(*controller));
181 controller->segment = seg;
185 static struct pci_bus *
186 scan_root_bus (int bus, struct pci_ops *ops, void *sysdata)
191 * We know this is a new root bus we haven't seen before, so
192 * scan it, even if we've seen the same bus number in a different
195 b = kmalloc(sizeof(*b), GFP_KERNEL);
199 memset(b, 0, sizeof(*b));
200 INIT_LIST_HEAD(&b->children);
201 INIT_LIST_HEAD(&b->devices);
203 list_add_tail(&b->node, &pci_root_buses);
205 b->number = b->secondary = bus;
206 b->resource[0] = &ioport_resource;
207 b->resource[1] = &iomem_resource;
209 b->sysdata = sysdata;
211 b->subordinate = pci_do_scan_bus(b);
217 alloc_resource (char *name, struct resource *root, unsigned long start, unsigned long end, unsigned long flags)
219 struct resource *res;
221 res = kmalloc(sizeof(*res), GFP_KERNEL);
225 memset(res, 0, sizeof(*res));
231 if (request_resource(root, res))
238 add_io_space (struct acpi_resource_address64 *addr)
244 if (addr->address_translation_offset == 0)
245 return IO_SPACE_BASE(0); /* part of legacy IO space */
247 if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION)
250 offset = (u64) ioremap(addr->address_translation_offset, 0);
251 for (i = 0; i < num_io_spaces; i++)
252 if (io_space[i].mmio_base == offset &&
253 io_space[i].sparse == sparse)
254 return IO_SPACE_BASE(i);
256 if (num_io_spaces == MAX_IO_SPACES) {
257 printk("Too many IO port spaces\n");
262 io_space[i].mmio_base = offset;
263 io_space[i].sparse = sparse;
265 return IO_SPACE_BASE(i);
269 count_window (struct acpi_resource *resource, void *data)
271 unsigned int *windows = (unsigned int *) data;
272 struct acpi_resource_address64 addr;
275 status = acpi_resource_to_address64(resource, &addr);
276 if (ACPI_SUCCESS(status))
277 if (addr.resource_type == ACPI_MEMORY_RANGE ||
278 addr.resource_type == ACPI_IO_RANGE)
284 struct pci_root_info {
285 struct pci_controller *controller;
290 add_window (struct acpi_resource *res, void *data)
292 struct pci_root_info *info = (struct pci_root_info *) data;
293 struct pci_window *window;
294 struct acpi_resource_address64 addr;
296 unsigned long flags, offset = 0;
297 struct resource *root;
299 status = acpi_resource_to_address64(res, &addr);
300 if (ACPI_SUCCESS(status)) {
301 if (!addr.address_length)
304 if (addr.resource_type == ACPI_MEMORY_RANGE) {
305 flags = IORESOURCE_MEM;
306 root = &iomem_resource;
307 offset = addr.address_translation_offset;
308 } else if (addr.resource_type == ACPI_IO_RANGE) {
309 flags = IORESOURCE_IO;
310 root = &ioport_resource;
311 offset = add_io_space(&addr);
317 window = &info->controller->window[info->controller->windows++];
318 window->resource.flags |= flags;
319 window->resource.start = addr.min_address_range;
320 window->resource.end = addr.max_address_range;
321 window->offset = offset;
323 if (alloc_resource(info->name, root, addr.min_address_range + offset,
324 addr.max_address_range + offset, flags))
325 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
326 addr.min_address_range + offset, addr.max_address_range + offset,
327 root->name, info->name);
334 pcibios_scan_root (void *handle, int seg, int bus)
336 struct pci_root_info info;
337 struct pci_controller *controller;
338 unsigned int windows = 0;
341 controller = alloc_pci_controller(seg);
345 controller->acpi_handle = handle;
347 acpi_walk_resources(handle, METHOD_NAME__CRS, count_window, &windows);
348 controller->window = kmalloc(sizeof(*controller->window) * windows, GFP_KERNEL);
349 if (!controller->window)
352 name = kmalloc(16, GFP_KERNEL);
356 sprintf(name, "PCI Bus %02x:%02x", seg, bus);
357 info.controller = controller;
359 acpi_walk_resources(handle, METHOD_NAME__CRS, add_window, &info);
361 return scan_root_bus(bus, pci_root_ops, controller);
364 kfree(controller->window);
372 pcibios_config_init (void)
377 printk("PCI: Using SAL to access configuration space\n");
379 pci_root_ops = &pci_sal_ops;
380 pci_config_read = pci_sal_read;
381 pci_config_write = pci_sal_write;
389 pcibios_config_init();
391 platform_pci_fixup(0); /* phase 0 fixups (before buses scanned) */
393 platform_pci_fixup(1); /* phase 1 fixups (after buses scanned) */
399 pcibios_fixup_device_resources (struct pci_dev *dev, struct pci_bus *bus)
401 struct pci_controller *controller = PCI_CONTROLLER(dev);
402 struct pci_window *window;
405 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
406 if (!dev->resource[i].start)
409 #define contains(win, res) ((res)->start >= (win)->start && \
410 (res)->end <= (win)->end)
412 for (j = 0; j < controller->windows; j++) {
413 window = &controller->window[j];
414 if (((dev->resource[i].flags & IORESOURCE_MEM &&
415 window->resource.flags & IORESOURCE_MEM) ||
416 (dev->resource[i].flags & IORESOURCE_IO &&
417 window->resource.flags & IORESOURCE_IO)) &&
418 contains(&window->resource, &dev->resource[i])) {
419 dev->resource[i].start += window->offset;
420 dev->resource[i].end += window->offset;
427 * Called after each bus is probed, but before its children are examined.
430 pcibios_fixup_bus (struct pci_bus *b)
432 struct list_head *ln;
434 for (ln = b->devices.next; ln != &b->devices; ln = ln->next)
435 pcibios_fixup_device_resources(pci_dev_b(ln), b);
439 pcibios_update_resource (struct pci_dev *dev, struct resource *root,
440 struct resource *res, int resource)
442 unsigned long where, size;
445 where = PCI_BASE_ADDRESS_0 + (resource * 4);
446 size = res->end - res->start;
447 pci_read_config_dword(dev, where, ®);
448 reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
449 pci_write_config_dword(dev, where, reg);
451 /* ??? FIXME -- record old value for shutdown. */
455 pcibios_update_irq (struct pci_dev *dev, int irq)
457 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
459 /* ??? FIXME -- record old value for shutdown. */
463 pcibios_fixup_pbus_ranges (struct pci_bus * bus, struct pbus_set_ranges_data * ranges)
465 ranges->io_start -= bus->resource[0]->start;
466 ranges->io_end -= bus->resource[0]->start;
467 ranges->mem_start -= bus->resource[1]->start;
468 ranges->mem_end -= bus->resource[1]->start;
472 pcibios_enable_resources (struct pci_dev *dev, int mask)
481 pci_read_config_word(dev, PCI_COMMAND, &cmd);
483 for (idx=0; idx<6; idx++) {
484 /* Only set up the desired resources. */
485 if (!(mask & (1 << idx)))
488 r = &dev->resource[idx];
489 if (!r->start && r->end) {
491 "PCI: Device %s not available because of resource collisions\n",
495 if (r->flags & IORESOURCE_IO)
496 cmd |= PCI_COMMAND_IO;
497 if (r->flags & IORESOURCE_MEM)
498 cmd |= PCI_COMMAND_MEMORY;
500 if (dev->resource[PCI_ROM_RESOURCE].start)
501 cmd |= PCI_COMMAND_MEMORY;
502 if (cmd != old_cmd) {
503 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
504 pci_write_config_word(dev, PCI_COMMAND, cmd);
510 pcibios_enable_device (struct pci_dev *dev, int mask)
514 ret = pcibios_enable_resources(dev, mask);
518 printk(KERN_INFO "PCI: Found IRQ %d for device %s\n", dev->irq, dev->slot_name);
524 pcibios_align_resource (void *data, struct resource *res,
525 unsigned long size, unsigned long align)
530 * PCI BIOS setup, always defaults to SAL interface
533 pcibios_setup (char *str)
539 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
540 enum pci_mmap_state mmap_state, int write_combine)
543 * I/O space cannot be accessed via normal processor loads and stores on this
546 if (mmap_state == pci_mmap_io)
548 * XXX we could relax this for I/O spaces for which ACPI indicates that
549 * the space is 1-to-1 mapped. But at the moment, we don't support
550 * multiple PCI address spaces and the legacy I/O space is not 1-to-1
551 * mapped, so this is moot.
556 * Leave vm_pgoff as-is, the PCI space address is the physical address on this
559 vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO);
562 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
564 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
566 if (remap_page_range(vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
567 vma->vm_end - vma->vm_start, vma->vm_page_prot))
574 * pci_cacheline_size - determine cacheline size for PCI devices
577 * We want to use the line-size of the outer-most cache. We assume
578 * that this line-size is the same for all CPUs.
580 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
582 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
585 pci_cacheline_size (void)
587 u64 levels, unique_caches;
589 pal_cache_config_info_t cci;
590 static u8 cacheline_size;
593 return cacheline_size;
595 status = ia64_pal_cache_summary(&levels, &unique_caches);
597 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
598 __FUNCTION__, status);
599 return SMP_CACHE_BYTES;
602 status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
605 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
606 __FUNCTION__, status);
607 return SMP_CACHE_BYTES;
609 cacheline_size = 1 << cci.pcci_line_size;
610 return cacheline_size;
614 * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
615 * @dev: the PCI device for which MWI is enabled
617 * For ia64, we can get the cacheline sizes from PAL.
619 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
622 pcibios_set_mwi (struct pci_dev *dev)
624 unsigned long desired_linesize, current_linesize;
628 desired_linesize = pci_cacheline_size();
630 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
631 current_linesize = 4 * pci_linesize;
632 if (desired_linesize != current_linesize) {
633 printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
634 dev->slot_name, current_linesize);
635 if (current_linesize > desired_linesize) {
636 printk(" expected %lu bytes instead\n", desired_linesize);
639 printk(" correcting to %lu\n", desired_linesize);
640 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);