2 * SMP boot-related support
4 * Copyright (C) 1998-2003 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * 01/05/16 Rohit Seth <rohit.seth@intel.com> Moved SMP booting functions from smp.c to here.
8 * 01/04/27 David Mosberger <davidm@hpl.hp.com> Added ITC synching code.
12 #define __KERNEL_SYSCALLS__
14 #include <linux/config.h>
16 #include <linux/bootmem.h>
17 #include <linux/delay.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/kernel.h>
22 #include <linux/kernel_stat.h>
24 #include <linux/smp.h>
25 #include <linux/smp_lock.h>
26 #include <linux/spinlock.h>
27 #include <linux/efi.h>
29 #include <asm/atomic.h>
30 #include <asm/bitops.h>
31 #include <asm/cache.h>
32 #include <asm/current.h>
33 #include <asm/delay.h>
36 #include <asm/machvec.h>
39 #include <asm/pgalloc.h>
40 #include <asm/pgtable.h>
41 #include <asm/processor.h>
42 #include <asm/ptrace.h>
44 #include <asm/system.h>
45 #include <asm/unistd.h>
50 #define Dprintk(x...) printk(x)
57 * ITC synchronization related stuff:
60 #define SLAVE (SMP_CACHE_BYTES/8)
62 #define NUM_ROUNDS 64 /* magic value */
63 #define NUM_ITERS 5 /* likewise */
65 static spinlock_t itc_sync_lock = SPIN_LOCK_UNLOCKED;
66 static volatile unsigned long go[SLAVE + 1];
68 #define DEBUG_ITC_SYNC 0
70 extern void __init calibrate_delay (void);
71 extern void start_ap (void);
72 extern unsigned long ia64_iobase;
76 /* Setup configured maximum number of CPUs to activate */
77 static int max_cpus = -1;
79 /* Total count of live CPUs */
82 /* Bitmask of currently online CPUs */
83 volatile unsigned long cpu_online_map;
85 /* which logical CPU number maps to which CPU (physical APIC ID) */
86 volatile int ia64_cpu_to_sapicid[NR_CPUS];
88 static volatile unsigned long cpu_callin_map;
90 struct smp_boot_data smp_boot_data __initdata;
92 /* Set when the idlers are all forked */
93 int smp_threads_ready;
95 unsigned long ap_wakeup_vector = -1; /* External Int use to wakeup APs */
97 char __initdata no_int_routing;
99 unsigned char smp_int_redirect; /* are INT and IPI redirectable by the chipset? */
102 * Setup routine for controlling SMP activation
104 * Command-line option of "nosmp" or "maxcpus=0" will disable SMP
105 * activation entirely (the MPS table probe still happens, though).
107 * Command-line option of "maxcpus=<NUM>", where <NUM> is an integer
108 * greater than 0, limits the maximum number of CPUs activated in
119 __setup("nosmp", nosmp);
124 get_option(&str, &max_cpus);
128 __setup("maxcpus=", maxcpus);
131 nointroute (char *str)
137 __setup("nointroute", nointroute);
140 sync_master (void *arg)
142 unsigned long flags, i;
146 local_irq_save(flags);
148 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) {
151 go[SLAVE] = ia64_get_itc();
154 local_irq_restore(flags);
158 * Return the number of cycles by which our itc differs from the itc on the master
159 * (time-keeper) CPU. A positive number indicates our itc is ahead of the master,
160 * negative that it is behind.
163 get_delta (long *rt, long *master)
165 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
166 unsigned long tcenter, t0, t1, tm;
169 for (i = 0; i < NUM_ITERS; ++i) {
172 while (!(tm = go[SLAVE]));
176 if (t1 - t0 < best_t1 - best_t0)
177 best_t0 = t0, best_t1 = t1, best_tm = tm;
180 *rt = best_t1 - best_t0;
181 *master = best_tm - best_t0;
183 /* average best_t0 and best_t1 without overflow: */
184 tcenter = (best_t0/2 + best_t1/2);
185 if (best_t0 % 2 + best_t1 % 2 == 2)
187 return tcenter - best_tm;
191 * Synchronize ar.itc of the current (slave) CPU with the ar.itc of the MASTER CPU
192 * (normally the time-keeper CPU). We use a closed loop to eliminate the possibility of
193 * unaccounted-for errors (such as getting a machine check in the middle of a calibration
194 * step). The basic idea is for the slave to ask the master what itc value it has and to
195 * read its own itc before and after the master responds. Each iteration gives us three
209 * The goal is to adjust the slave's ar.itc such that tm falls exactly half-way between t0
210 * and t1. If we achieve this, the clocks are synchronized provided the interconnect
211 * between the slave and the master is symmetric. Even if the interconnect were
212 * asymmetric, we would still know that the synchronization error is smaller than the
213 * roundtrip latency (t0 - t1).
215 * When the interconnect is quiet and symmetric, this lets us synchronize the itc to
216 * within one or two cycles. However, we can only *guarantee* that the synchronization is
217 * accurate to within a round-trip time, which is typically in the range of several
218 * hundred cycles (e.g., ~500 cycles). In practice, this means that the itc's are usually
219 * almost perfectly synchronized, but we shouldn't assume that the accuracy is much better
220 * than half a micro second or so.
223 ia64_sync_itc (unsigned int master)
225 long i, delta, adj, adjust_latency = 0, done = 0;
226 unsigned long flags, rt, master_time_stamp, bound;
229 long rt; /* roundtrip time */
230 long master; /* master's timestamp */
231 long diff; /* difference between midpoint and master's timestamp */
232 long lat; /* estimate of itc adjustment latency */
238 if (smp_call_function_single(master, sync_master, NULL, 1, 0) < 0) {
239 printk(KERN_ERR "sync_itc: failed to get attention of CPU %u!\n", master);
243 while (go[MASTER]); /* wait for master to be ready */
245 spin_lock_irqsave(&itc_sync_lock, flags);
247 for (i = 0; i < NUM_ROUNDS; ++i) {
248 delta = get_delta(&rt, &master_time_stamp);
250 done = 1; /* let's lock on to this... */
256 adjust_latency += -delta;
257 adj = -delta + adjust_latency/4;
261 ia64_set_itc(ia64_get_itc() + adj);
265 t[i].master = master_time_stamp;
267 t[i].lat = adjust_latency/4;
271 spin_unlock_irqrestore(&itc_sync_lock, flags);
274 for (i = 0; i < NUM_ROUNDS; ++i)
275 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
276 t[i].rt, t[i].master, t[i].diff, t[i].lat);
279 printk(KERN_INFO "CPU %d: synchronized ITC with CPU %u (last diff %ld cycles, "
280 "maxerr %lu cycles)\n", smp_processor_id(), master, delta, rt);
284 * Ideally sets up per-cpu profiling hooks. Doesn't do much now...
286 static inline void __init
287 smp_setup_percpu_timer (void)
289 local_cpu_data->prof_counter = 1;
290 local_cpu_data->prof_multiplier = 1;
294 * Architecture specific routine called by the kernel just before init is
295 * fired off. This allows the BP to have everything in order [we hope].
296 * At the end of this all the APs will hit the system scheduling and off
297 * we go. Each AP will jump through the kernel
298 * init into idle(). At this point the scheduler will one day take over
299 * and give them jobs to do. smp_callin is a standard routine
300 * we use to track CPUs as they power up.
303 static volatile atomic_t smp_commenced = ATOMIC_INIT(0);
309 * Lets the callins below out of their loop.
311 Dprintk("Setting commenced=1, go go go\n");
314 atomic_set(&smp_commenced,1);
322 extern void ia64_init_itm(void);
323 extern void ia64_cpu_local_tick(void);
325 #ifdef CONFIG_PERFMON
326 extern void pfm_init_percpu(void);
329 cpuid = smp_processor_id();
330 phys_id = hard_smp_processor_id();
332 if (test_and_set_bit(cpuid, &cpu_online_map)) {
333 printk(KERN_ERR "huh, phys CPU#0x%x, CPU#0x%x already present??\n",
338 smp_setup_percpu_timer();
346 * Set I/O port base per CPU
348 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
350 #ifdef CONFIG_IA64_MCA
351 ia64_mca_cmc_vector_setup(); /* Setup vector on AP & enable */
354 #ifdef CONFIG_PERFMON
360 local_cpu_data->loops_per_jiffy = loops_per_jiffy;
362 if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) {
364 * Synchronize the ITC with the BP. Need to do this after irqs are
365 * enabled because ia64_sync_itc() calls smp_call_function_single(), which
366 * calls spin_unlock_bh(), which calls spin_unlock_bh(), which calls
367 * local_bh_enable(), which bugs out if irqs are not enabled...
369 Dprintk("Going to syncup ITC with BP.\n");
373 * Make sure we didn't sync the itc ahead of the next
374 * timer interrupt, if so, just reset it.
376 if (time_after(ia64_get_itc(),local_cpu_data->itm_next)) {
377 Dprintk("oops, jumped a timer.\n");
378 ia64_cpu_local_tick();
383 * Allow the master to continue.
385 set_bit(cpuid, &cpu_callin_map);
386 Dprintk("Stack on CPU %d at about %p\n",cpuid, &cpuid);
391 * Activate a secondary processor. head.S calls this.
394 start_secondary (void *unused)
396 extern int cpu_idle (void);
398 Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id());
402 Dprintk("CPU %d is set to go.\n", smp_processor_id());
403 while (!atomic_read(&smp_commenced))
406 Dprintk("CPU %d is starting idle.\n", smp_processor_id());
414 * don't care about the eip and regs settings since we'll never reschedule the
417 return do_fork(CLONE_VM|CLONE_PID, 0, 0, 0);
421 do_boot_cpu (int sapicid)
423 struct task_struct *idle;
428 * We can't use kernel_thread since we must avoid to
429 * reschedule the child.
431 if (fork_by_hand() < 0)
432 panic("failed fork for CPU %d", cpu);
435 * We remove it from the pidhash and the runqueue
436 * once we got the process:
438 idle = init_task.prev_task;
440 panic("No idle process for CPU %d", cpu);
442 task_set_cpu(idle, cpu); /* we schedule the first task manually */
444 ia64_cpu_to_sapicid[cpu] = sapicid;
446 del_from_runqueue(idle);
447 unhash_process(idle);
448 init_tasks[cpu] = idle;
450 Dprintk("Sending wakeup vector %lu to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid);
452 platform_send_ipi(cpu, ap_wakeup_vector, IA64_IPI_DM_INT, 0);
455 * Wait 10s total for the AP to start
457 Dprintk("Waiting on callin_map ...");
458 for (timeout = 0; timeout < 100000; timeout++) {
459 if (test_bit(cpu, &cpu_callin_map))
460 break; /* It has booted */
465 if (test_bit(cpu, &cpu_callin_map)) {
466 /* number CPUs logically, starting from 1 (BSP is 0) */
467 printk(KERN_INFO "CPU%d: CPU has booted.\n", cpu);
469 printk(KERN_ERR "Processor 0x%x/0x%x is stuck.\n", cpu, sapicid);
470 ia64_cpu_to_sapicid[cpu] = -1;
476 * Cycle through the APs sending Wakeup IPIs to boot each.
482 int boot_cpu_id = hard_smp_processor_id();
485 * Initialize the logical to physical CPU number mapping
486 * and the per-CPU profiling counter/multiplier
489 for (cpu = 0; cpu < NR_CPUS; cpu++)
490 ia64_cpu_to_sapicid[cpu] = -1;
491 smp_setup_percpu_timer();
494 * We have the boot CPU online for sure.
496 set_bit(0, &cpu_online_map);
497 set_bit(0, &cpu_callin_map);
499 local_cpu_data->loops_per_jiffy = loops_per_jiffy;
500 ia64_cpu_to_sapicid[0] = boot_cpu_id;
502 printk(KERN_INFO "Boot processor id 0x%x/0x%x\n", 0, boot_cpu_id);
504 global_irq_holder = 0;
505 current->processor = 0;
509 * If SMP should be disabled, then really disable it!
511 if (!max_cpus || (max_cpus < -1)) {
512 printk(KERN_INFO "SMP mode deactivated.\n");
518 printk(KERN_INFO "Limiting CPUs to %d\n", max_cpus);
520 if (smp_boot_data.cpu_count > 1) {
522 printk(KERN_INFO "SMP: starting up secondaries.\n");
524 for (cpu = 0; cpu < smp_boot_data.cpu_count; cpu++) {
526 * Don't even attempt to start the boot CPU!
528 sapicid = smp_boot_data.cpu_phys_id[cpu];
529 if ((sapicid == -1) || (sapicid == hard_smp_processor_id()))
532 if ((max_cpus > 0) && (cpucount + 1 >= max_cpus))
535 do_boot_cpu(sapicid);
538 smp_num_cpus = cpucount + 1;
541 * Allow the user to impress friends.
544 printk("Before bogomips.\n");
546 printk(KERN_WARNING "Warning: only one processor found.\n");
548 unsigned long bogosum = 0;
549 for (cpu = 0; cpu < NR_CPUS; cpu++)
550 if (cpu_online_map & (1UL << cpu))
551 bogosum += cpu_data(cpu)->loops_per_jiffy;
553 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
554 cpucount + 1, bogosum/(500000/HZ), (bogosum/(5000/HZ))%100);
562 * Assume that CPU's have been discovered by some platform-dependent interface. For
563 * SoftSDV/Lion, that would be ACPI.
565 * Setup of the IPI irq handler is done in irq.c:init_IRQ_SMP().
568 init_smp_config(void)
576 /* Tell SAL where to drop the AP's. */
577 ap_startup = (struct fptr *) start_ap;
578 sal_ret = ia64_sal_set_vectors(SAL_VECTOR_OS_BOOT_RENDEZ,
579 ia64_tpa(ap_startup->fp), ia64_tpa(ap_startup->gp), 0, 0, 0, 0);
581 printk(KERN_ERR "SMP: Can't set SAL AP Boot Rendezvous: %s\n Forcing UP mode\n",
582 ia64_sal_strerror(sal_ret));
589 * Initialize the logical CPU number to SAPICID mapping
592 smp_build_cpu_map (void)
595 int boot_cpu_id = hard_smp_processor_id();
597 for (cpu = 0; cpu < NR_CPUS; cpu++)
598 ia64_cpu_to_sapicid[cpu] = -1;
600 ia64_cpu_to_sapicid[0] = boot_cpu_id;
602 for (cpu = 1, i = 0; i < smp_boot_data.cpu_count; i++) {
603 sapicid = smp_boot_data.cpu_phys_id[i];
604 if (sapicid == boot_cpu_id)
606 ia64_cpu_to_sapicid[cpu] = sapicid;