3 * BRIEF MODULE DESCRIPTION
4 * ITE 8172G interrupt/setup routines.
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
10 * Part of this file was derived from Carsten Langgaard's
11 * arch/mips/mips-boards/atlas/atlas_int.c.
13 * Carsten Langgaard, carstenl@mips.com
14 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 #include <linux/config.h>
37 #include <linux/errno.h>
38 #include <linux/init.h>
39 #include <linux/irq.h>
40 #include <linux/kernel_stat.h>
41 #include <linux/module.h>
42 #include <linux/signal.h>
43 #include <linux/sched.h>
44 #include <linux/types.h>
45 #include <linux/interrupt.h>
46 #include <linux/ioport.h>
47 #include <linux/timex.h>
48 #include <linux/slab.h>
49 #include <linux/random.h>
50 #include <linux/serial_reg.h>
52 #include <asm/bitops.h>
53 #include <asm/bootinfo.h>
55 #include <asm/mipsregs.h>
56 #include <asm/system.h>
57 #include <asm/it8172/it8172.h>
58 #include <asm/it8172/it8172_int.h>
59 #include <asm/it8172/it8172_dbg.h>
63 /* note: prints function name for you */
64 #define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
66 #define DPRINTK(fmt, args...)
70 extern void breakpoint(void);
74 #define EXT_IRQ0_TO_IP 2 /* IP 2 */
75 #define EXT_IRQ5_TO_IP 7 /* IP 7 */
77 #define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
79 unsigned int local_bh_count[NR_CPUS];
80 unsigned int local_irq_count[NR_CPUS];
81 void disable_it8172_irq(unsigned int irq_nr);
82 void enable_it8172_irq(unsigned int irq_nr);
84 extern void set_debug_traps(void);
85 extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
86 extern asmlinkage void it8172_IRQ(void);
88 struct it8172_intc_regs volatile *it8172_hw0_icregs
89 = (struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE));
91 /* Function for careful CP0 interrupt mask access */
92 static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
94 unsigned long status = read_c0_status();
95 status &= ~((clr_mask & 0xFF) << 8);
96 status |= (set_mask & 0xFF) << 8;
97 write_c0_status(status);
100 static inline void mask_irq(unsigned int irq_nr)
102 modify_cp0_intmask(irq_nr, 0);
105 static inline void unmask_irq(unsigned int irq_nr)
107 modify_cp0_intmask(0, irq_nr);
110 void local_disable_irq(unsigned int irq_nr)
115 disable_it8172_irq(irq_nr);
116 restore_flags(flags);
119 void local_enable_irq(unsigned int irq_nr)
124 enable_it8172_irq(irq_nr);
125 restore_flags(flags);
129 void disable_it8172_irq(unsigned int irq_nr)
131 DPRINTK("disable_it8172_irq %d\n", irq_nr);
133 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
135 DPRINTK("DB lpc_mask %x\n", it8172_hw0_icregs->lpc_mask);
136 it8172_hw0_icregs->lpc_mask |=
137 (1 << (irq_nr - IT8172_LPC_IRQ_BASE));
138 DPRINTK("DA lpc_mask %x\n", it8172_hw0_icregs->lpc_mask);
140 else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
141 /* Local Bus interrupt */
142 DPRINTK("DB lb_mask %x\n", it8172_hw0_icregs->lb_mask);
143 it8172_hw0_icregs->lb_mask |=
144 (1 << (irq_nr - IT8172_LB_IRQ_BASE));
145 DPRINTK("DA lb_mask %x\n", it8172_hw0_icregs->lb_mask);
147 else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
148 /* PCI and other interrupts */
149 DPRINTK("DB pci_mask %x\n", it8172_hw0_icregs->pci_mask);
150 it8172_hw0_icregs->pci_mask |=
151 (1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
152 DPRINTK("DA pci_mask %x\n", it8172_hw0_icregs->pci_mask);
154 else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
156 DPRINTK("DB nmi_mask %x\n", it8172_hw0_icregs->nmi_mask);
157 it8172_hw0_icregs->nmi_mask |=
158 (1 << (irq_nr - IT8172_NMI_IRQ_BASE));
159 DPRINTK("DA nmi_mask %x\n", it8172_hw0_icregs->nmi_mask);
162 panic("disable_it8172_irq: bad irq %d", irq_nr);
166 void enable_it8172_irq(unsigned int irq_nr)
168 DPRINTK("enable_it8172_irq %d\n", irq_nr);
169 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
171 DPRINTK("EB before lpc_mask %x\n", it8172_hw0_icregs->lpc_mask);
172 it8172_hw0_icregs->lpc_mask &=
173 ~(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
174 DPRINTK("EA after lpc_mask %x\n", it8172_hw0_icregs->lpc_mask);
176 else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
177 /* Local Bus interrupt */
178 DPRINTK("EB lb_mask %x\n", it8172_hw0_icregs->lb_mask);
179 it8172_hw0_icregs->lb_mask &=
180 ~(1 << (irq_nr - IT8172_LB_IRQ_BASE));
181 DPRINTK("EA lb_mask %x\n", it8172_hw0_icregs->lb_mask);
183 else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
184 /* PCI and other interrupts */
185 DPRINTK("EB pci_mask %x\n", it8172_hw0_icregs->pci_mask);
186 it8172_hw0_icregs->pci_mask &=
187 ~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
188 DPRINTK("EA pci_mask %x\n", it8172_hw0_icregs->pci_mask);
190 else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
192 DPRINTK("EB nmi_mask %x\n", it8172_hw0_icregs->nmi_mask);
193 it8172_hw0_icregs->nmi_mask &=
194 ~(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
195 DPRINTK("EA nmi_mask %x\n", it8172_hw0_icregs->nmi_mask);
198 panic("enable_it8172_irq: bad irq %d", irq_nr);
202 static unsigned int startup_ite_irq(unsigned int irq)
204 enable_it8172_irq(irq);
208 #define shutdown_ite_irq disable_it8172_irq
209 #define mask_and_ack_ite_irq disable_it8172_irq
211 static void end_ite_irq(unsigned int irq)
213 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
214 enable_it8172_irq(irq);
217 static struct hw_interrupt_type it8172_irq_type = {
223 mask_and_ack_ite_irq,
229 static void enable_none(unsigned int irq) { }
230 static unsigned int startup_none(unsigned int irq) { return 0; }
231 static void disable_none(unsigned int irq) { }
232 static void ack_none(unsigned int irq) { }
234 /* startup is the same as "enable", shutdown is same as "disable" */
235 #define shutdown_none disable_none
236 #define end_none enable_none
238 static struct hw_interrupt_type cp0_irq_type = {
249 void enable_cpu_timer(void)
254 unmask_irq(1<<EXT_IRQ5_TO_IP); /* timer interrupt */
255 restore_flags(flags);
259 void __init init_IRQ(void)
264 memset(irq_desc, 0, sizeof(irq_desc));
265 set_except_vector(0, it8172_IRQ);
269 /* mask all interrupts */
270 it8172_hw0_icregs->lb_mask = 0xffff;
271 it8172_hw0_icregs->lpc_mask = 0xffff;
272 it8172_hw0_icregs->pci_mask = 0xffff;
273 it8172_hw0_icregs->nmi_mask = 0xffff;
275 /* make all interrupts level triggered */
276 it8172_hw0_icregs->lb_trigger = 0;
277 it8172_hw0_icregs->lpc_trigger = 0;
278 it8172_hw0_icregs->pci_trigger = 0;
279 it8172_hw0_icregs->nmi_trigger = 0;
281 /* active level setting */
282 /* uart, keyboard, and mouse are active high */
283 it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000);
284 it8172_hw0_icregs->lb_level |= 0x20;
286 /* keyboard and mouse are edge triggered */
287 it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000);
291 // Enable this piece of code to make internal USB interrupt
293 it8172_hw0_icregs->pci_trigger |=
294 (1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
295 it8172_hw0_icregs->pci_level &=
296 ~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
299 for (i = 0; i <= IT8172_LAST_IRQ; i++) {
300 irq_desc[i].handler = &it8172_irq_type;
302 irq_desc[MIPS_CPU_TIMER_IRQ].handler = &cp0_irq_type;
303 set_c0_status(ALLINTS_NOTIMER);
306 /* If local serial I/O used for debug port, enter kgdb at once */
307 puts("Waiting for kgdb to connect...");
313 void mips_spurious_interrupt(struct pt_regs *regs)
318 unsigned long status, cause;
320 printk("got spurious interrupt\n");
321 status = read_c0_status();
322 cause = read_c0_cause();
323 printk("status %x cause %x\n", status, cause);
324 printk("epc %x badvaddr %x \n", regs->cp0_epc, regs->cp0_badvaddr);
329 void it8172_hw0_irqdispatch(struct pt_regs *regs)
332 unsigned short intstatus = 0, status = 0;
334 intstatus = it8172_hw0_icregs->intstatus;
335 if (intstatus & 0x8) {
336 panic("Got NMI interrupt");
338 else if (intstatus & 0x4) {
341 status |= it8172_hw0_icregs->pci_req;
342 while (!(status & 0x1)) {
346 irq += IT8172_PCI_DEV_IRQ_BASE;
347 //printk("pci int %d\n", irq);
349 else if (intstatus & 0x1) {
350 /* Local Bus interrupt */
352 status |= it8172_hw0_icregs->lb_req;
353 while (!(status & 0x1)) {
357 irq += IT8172_LB_IRQ_BASE;
358 //printk("lb int %d\n", irq);
360 else if (intstatus & 0x2) {
362 /* Since some lpc interrupts are edge triggered,
363 * we could lose an interrupt this way because
364 * we acknowledge all ints at onces. Revisit.
366 status |= it8172_hw0_icregs->lpc_req;
367 it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */
369 while (!(status & 0x1)) {
373 irq += IT8172_LPC_IRQ_BASE;
374 //printk("LPC int %d\n", irq);
382 void show_pending_irqs(void)
384 fputs("intstatus: ");
385 put32(it8172_hw0_icregs->intstatus);
389 put32(it8172_hw0_icregs->pci_req);
393 put32(it8172_hw0_icregs->lb_req);
397 put32(it8172_hw0_icregs->lpc_req);