arch/mips/momentum/ocelot_c/setup.c

   1 /*
   2  * setup.c
   3  *
   4  * BRIEF MODULE DESCRIPTION
   5  * Momentum Computer Ocelot-C and -CS board dependent boot routines
   6  *
   7  * Copyright (C) 1996, 1997, 2001  Ralf Baechle
   8  * Copyright (C) 2000 RidgeRun, Inc.
   9  * Copyright (C) 2001 Red Hat, Inc.
  10  * Copyright (C) 2002 Momentum Computer
  11  *
  12  * Author: Matthew Dharm, Momentum Computer
  13  *   mdharm@momenco.com
  14  *
  15  * Louis Hamilton, Red Hat, Inc.
  16  *   hamilton@redhat.com  [MIPS64 modifications]
  17  *
  18  * Author: RidgeRun, Inc.
  19  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  20  *
  21  * Copyright 2001 MontaVista Software Inc.
  22  * Author: jsun@mvista.com or jsun@junsun.net
  23  *
  24  *  This program is free software; you can redistribute  it and/or modify it
  25  *  under  the terms of  the GNU General  Public License as published by the
  26  *  Free Software Foundation;  either version 2 of the  License, or (at your
  27  *  option) any later version.
  28  *
  29  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  30  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  31  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  32  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  33  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  34  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  35  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  36  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  37  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  38  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  *  You should have received a copy of the  GNU General Public License along
  41  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  42  *  675 Mass Ave, Cambridge, MA 02139, USA.
  43  *
  44  */
  45 #include <linux/init.h>
  46 #include <linux/kernel.h>
  47 #include <linux/types.h>
  48 #include <linux/mc146818rtc.h>
  49 #include <linux/mm.h>
  50 #include <linux/swap.h>
  51 #include <linux/ioport.h>
  52 #include <linux/sched.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/pci.h>
  55 #include <linux/timex.h>
  56 #include <linux/vmalloc.h>
  57 #include <asm/time.h>
  58 #include <asm/bootinfo.h>
  59 #include <asm/page.h>
  60 #include <asm/bootinfo.h>
  61 #include <asm/io.h>
  62 #include <asm/irq.h>
  63 #include <asm/pci.h>
  64 #include <asm/processor.h>
  65 #include <asm/ptrace.h>
  66 #include <asm/reboot.h>
  67 #include <asm/mc146818rtc.h>
  68 #include <linux/version.h>
  69 #include <linux/bootmem.h>
  70 #include <linux/blk.h>
  71 #include <asm/mv64340.h>
  72 #include "ocelot_c_fpga.h"
  73
  74 unsigned long mv64340_base;
  75 extern unsigned long mv64340_sram_base;
  76 unsigned long cpu_clock;
  77
  78 /* These functions are used for rebooting or halting the machine*/
  79 extern void momenco_ocelot_restart(char *command);
  80 extern void momenco_ocelot_halt(void);
  81 extern void momenco_ocelot_power_off(void);
  82
  83 void momenco_time_init(void);
  84
  85 static char reset_reason;
  86
  87 void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask);
  88 #define ENTRYLO(x) ((pte_val(mk_pte_phys((x), PAGE_KERNEL_UNCACHED)) >> 6)|1)
  89
  90 /* setup code for a handoff from a version 2 PMON 2000 PROM */
  91 void PMON_v2_setup(void)
  92 {
  93         /* Some wired TLB entries for the MV64340 and perhiperals. The
  94            MV64340 is going to be hit on every IRQ anyway - there's
  95            absolutely no point in letting it be a random TLB entry, as
  96            it'll just cause needless churning of the TLB. And we use
  97            the other half for the serial port, which is just a PITA
  98            otherwise :)
  99
 100                 Device                  Physical        Virtual
 101                 MV64340 Internal Regs   0xf4000000      0xf4000000
 102                 Ocelot-C[S] PLD (CS0)   0xfc000000      0xfc000000
 103                 NVRAM (CS1)             0xfc800000      0xfc800000
 104                 UARTs (CS2)             0xfd000000      0xfd000000
 105                 Internal SRAM           0xfe000000      0xfe000000
 106                 M-Systems DOC (CS3)     0xff000000      0xff000000
 107         */
 108   printk("PMON_v2_setup\n");
 109
 110 #ifdef CONFIG_MIPS64
 111         /* marvell and extra space */
 112         add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
 113         /* fpga, rtc, and uart */
 114         add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M);
 115         /* m-sys and internal SRAM */
 116         add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
 117
 118         mv64340_base = 0xfffffffff4000000;
 119         mv64340_sram_base = 0xfffffffffe000000;
 120 #else
 121         /* marvell and extra space */
 122         add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
 123         /* fpga, rtc, and uart */
 124         add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
 125         /* m-sys and internal SRAM */
 126         add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
 127
 128         mv64340_base = 0xf4000000;
 129         mv64340_sram_base = 0xfe000000;
 130 #endif
 131 }
 132
 133 #define CONV_BCD_TO_BIN(val)    (((val) & 0xf) + (((val) >> 4) * 10))
 134 #define CONV_BIN_TO_BCD(val)    (((val) % 10) + (((val) / 10) << 4))
 135
 136 unsigned long m48t37y_get_time(void)
 137 {
 138 #ifdef CONFIG_MIPS64
 139         unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
 140 #else
 141         unsigned char* rtc_base = (unsigned char*)0xfc800000;
 142 #endif
 143         unsigned int year, month, day, hour, min, sec;
 144
 145         /* stop the update */
 146         rtc_base[0x7ff8] = 0x40;
 147
 148         year = CONV_BCD_TO_BIN(rtc_base[0x7fff]);
 149         year += CONV_BCD_TO_BIN(rtc_base[0x7ff1]) * 100;
 150
 151         month = CONV_BCD_TO_BIN(rtc_base[0x7ffe]);
 152
 153         day = CONV_BCD_TO_BIN(rtc_base[0x7ffd]);
 154
 155         hour = CONV_BCD_TO_BIN(rtc_base[0x7ffb]);
 156         min = CONV_BCD_TO_BIN(rtc_base[0x7ffa]);
 157         sec = CONV_BCD_TO_BIN(rtc_base[0x7ff9]);
 158
 159         /* start the update */
 160         rtc_base[0x7ff8] = 0x00;
 161
 162         return mktime(year, month, day, hour, min, sec);
 163 }
 164
 165 int m48t37y_set_time(unsigned long sec)
 166 {
 167 #ifdef CONFIG_MIPS64
 168         unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
 169 #else
 170         unsigned char* rtc_base = (unsigned char*)0xfc800000;
 171 #endif
 172         struct rtc_time tm;
 173
 174         /* convert to a more useful format -- note months count from 0 */
 175         to_tm(sec, &tm);
 176         tm.tm_mon += 1;
 177
 178         /* enable writing */
 179         rtc_base[0x7ff8] = 0x80;
 180
 181         /* year */
 182         rtc_base[0x7fff] = CONV_BIN_TO_BCD(tm.tm_year % 100);
 183         rtc_base[0x7ff1] = CONV_BIN_TO_BCD(tm.tm_year / 100);
 184
 185         /* month */
 186         rtc_base[0x7ffe] = CONV_BIN_TO_BCD(tm.tm_mon);
 187
 188         /* day */
 189         rtc_base[0x7ffd] = CONV_BIN_TO_BCD(tm.tm_mday);
 190
 191         /* hour/min/sec */
 192         rtc_base[0x7ffb] = CONV_BIN_TO_BCD(tm.tm_hour);
 193         rtc_base[0x7ffa] = CONV_BIN_TO_BCD(tm.tm_min);
 194         rtc_base[0x7ff9] = CONV_BIN_TO_BCD(tm.tm_sec);
 195
 196         /* day of week -- not really used, but let's keep it up-to-date */
 197         rtc_base[0x7ffc] = CONV_BIN_TO_BCD(tm.tm_wday + 1);
 198
 199         /* disable writing */
 200         rtc_base[0x7ff8] = 0x00;
 201
 202         return 0;
 203 }
 204
 205 void momenco_timer_setup(struct irqaction *irq)
 206 {
 207         setup_irq(7, irq);
 208 }
 209
 210 void momenco_time_init(void)
 211 {
 212 #ifdef CONFIG_CPU_SR71000
 213         mips_hpt_frequency = cpu_clock;
 214 #elif defined(CONFIG_CPU_RM7000)
 215         mips_hpt_frequency = cpu_clock / 2;
 216 #else
 217 #error Unknown CPU for this board
 218 #endif
 219         printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
 220         board_timer_setup = momenco_timer_setup;
 221
 222         rtc_get_time = m48t37y_get_time;
 223         rtc_set_time = m48t37y_set_time;
 224 }
 225
 226 void __init momenco_ocelot_c_setup(void)
 227 {
 228         unsigned int tmpword;
 229
 230         board_time_init = momenco_time_init;
 231
 232         _machine_restart = momenco_ocelot_restart;
 233         _machine_halt = momenco_ocelot_halt;
 234         _machine_power_off = momenco_ocelot_power_off;
 235
 236         /*
 237          * initrd_start = (ulong)ocelot_initrd_start;
 238          * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
 239          * initrd_below_start_ok = 1;
 240          */
 241
 242         /* do handoff reconfiguration */
 243         PMON_v2_setup();
 244
 245         /* shut down ethernet ports, just to be sure our memory doesn't get
 246          * corrupted by random ethernet traffic.
 247          */
 248         MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
 249         MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
 250         MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
 251         MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
 252         do {}
 253           while (MV_READ_DATA(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
 254         do {}
 255           while (MV_READ_DATA(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
 256         do {}
 257           while (MV_READ_DATA(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
 258         do {}
 259           while (MV_READ_DATA(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
 260         MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), MV_READ_DATA(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
 261         MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), MV_READ_DATA(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
 262
 263         /* Turn off the Bit-Error LED */
 264         OCELOT_FPGA_WRITE(0x80, CLR);
 265
 266         tmpword = OCELOT_FPGA_READ(BOARDREV);
 267 #ifdef CONFIG_CPU_SR71000
 268         if (tmpword < 26)
 269                 printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
 270                         'A'+tmpword);
 271         else
 272                 printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
 273                         tmpword);
 274 #else
 275         if (tmpword < 26)
 276                 printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
 277                         'A'+tmpword);
 278         else
 279                 printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
 280                         tmpword);
 281 #endif
 282
 283         tmpword = OCELOT_FPGA_READ(FPGA_REV);
 284         printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
 285         tmpword = OCELOT_FPGA_READ(RESET_STATUS);
 286         printk("Reset reason: 0x%x\n", tmpword);
 287         switch (tmpword) {
 288                 case 0x1:
 289                         printk("  - Power-up reset\n");
 290                         break;
 291                 case 0x2:
 292                         printk("  - Push-button reset\n");
 293                         break;
 294                 case 0x4:
 295                         printk("  - cPCI bus reset\n");
 296                         break;
 297                 case 0x8:
 298                         printk("  - Watchdog reset\n");
 299                         break;
 300                 case 0x10:
 301                         printk("  - Software reset\n");
 302                         break;
 303                 default:
 304                         printk("  - Unknown reset cause\n");
 305         }
 306         reset_reason = tmpword;
 307         OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
 308
 309         tmpword = OCELOT_FPGA_READ(CPCI_ID);
 310         printk("cPCI ID register: 0x%02x\n", tmpword);
 311         printk("  - Slot number: %d\n", tmpword & 0x1f);
 312         printk("  - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
 313         printk("  - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
 314
 315         tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
 316         printk("Board Status register: 0x%02x\n", tmpword);
 317         printk("  - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
 318         printk("  - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
 319         printk("  - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
 320         printk("  - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
 321
 322         switch(tmpword &3) {
 323         case 3:
 324                 /* 512MiB */
 325                 add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
 326                 break;
 327         case 2:
 328                 /* 256MiB */
 329                 add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
 330                 break;
 331         case 1:
 332                 /* 128MiB */
 333                 add_memory_region(0x0,  0x80<<20, BOOT_MEM_RAM);
 334                 break;
 335         case 0:
 336                 /* 1GiB -- needs CONFIG_HIGHMEM */
 337                 add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
 338                 break;
 339         }
 340 }
 341
 342 #ifndef CONFIG_MIPS64
 343 /* This needs to be one of the first initcalls, because no I/O port access
 344    can work before this */
 345 static int io_base_ioremap(void)
 346 {
 347         /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
 348         void *io_remap_range = ioremap(0xc0000000, 0x30000000);
 349
 350         if (!io_remap_range) {
 351                 panic("Could not ioremap I/O port range");
 352         }
 353         printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range);
 354         set_io_port_base(io_remap_range - 0xc0000000);
 355
 356         return 0;
 357 }
 358
 359 module_init(io_base_ioremap);
 360 #endif