3 * Copyright 2002 Momentum Computer
4 * Author: mdharm@momenco.com
6 * arch/mips/momentum/ocelot_g/gt_irq.c
7 * Interrupt routines for gt64240. Currently it only handles timer irq.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <asm/ptrace.h>
18 #include <linux/config.h>
19 #include <linux/sched.h>
20 #include <linux/kernel_stat.h>
24 unsigned long bus_clock;
27 * These are interrupt handlers for the GT on-chip interrupts. They
28 * all come in to the MIPS on a single interrupt line, and have to
29 * be handled and ack'ed differently than other MIPS interrupts.
34 struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
35 void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
38 * Hooks IRQ handler to the system. When the system is interrupted
39 * the interrupt service routine is called.
42 * int_cause - The interrupt cause number. In EVB64120 two parameters
43 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
44 * bit_num - Indicates which bit number in the cause register
45 * isr_ptr - Pointer to the interrupt service routine
47 void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr)
49 irq_handlers[int_cause][bit_num].routine = isr_ptr;
54 * Enables the IRQ on Galileo Chip
57 * int_cause - The interrupt cause number. In EVB64120 two parameters
58 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
59 * bit_num - Indicates which bit number in the cause register
62 * 1 if succesful, 0 if failure
64 int enable_galileo_irq(int int_cause, int bit_num)
66 if (int_cause == INT_CAUSE_MAIN)
67 SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num));
68 else if (int_cause == INT_CAUSE_HIGH)
69 SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
78 * Disables the IRQ on Galileo Chip
81 * int_cause - The interrupt cause number. In EVB64120 two parameters
82 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
83 * bit_num - Indicates which bit number in the cause register
86 * 1 if succesful, 0 if failure
88 int disable_galileo_irq(int int_cause, int bit_num)
90 if (int_cause == INT_CAUSE_MAIN)
91 RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER,
93 else if (int_cause == INT_CAUSE_HIGH)
94 RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
103 * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#.
105 * We route the timer interrupt to P0_INT# (IRQ 6), and that's all this
106 * routine can handle, for now.
108 * In the future, we'll route more interrupts to this pin, and that's why
109 * we keep this particular structure in the function.
112 static void gt64240_p0int_irq(int irq, void *dev_id, struct pt_regs *regs)
114 uint32_t irq_src, irq_src_mask;
117 /* get the low interrupt cause register */
118 GT_READ(LOW_INTERRUPT_CAUSE_REGISTER, &irq_src);
120 /* get the mask register for this pin */
121 GT_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, &irq_src_mask);
123 /* mask off only the interrupts we're interested in */
124 irq_src = irq_src & irq_src_mask;
128 /* Check for timer interrupt */
129 if (irq_src & 0x00000100) {
131 irq_src &= ~0x00000100;
133 /* Clear any pending cause bits */
134 GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
136 /* handle the timer call */
142 "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n",
148 * Interrupt handler for interrupts coming from the Galileo chip.
149 * It could be built in ethernet ports etc...
151 static void gt64240_irq(int irq, void *dev_id, struct pt_regs *regs)
153 unsigned int irq_src, int_high_src, irq_src_mask,
158 GT_READ(GT_INTRCAUSE_OFS, &irq_src);
159 GT_READ(GT_INTRMASK_OFS, &irq_src_mask);
160 GT_READ(GT_HINTRCAUSE_OFS, &int_high_src);
161 GT_READ(GT_HINTRMASK_OFS, &int_high_src_mask);
163 irq_src = irq_src & irq_src_mask;
164 int_high_src = int_high_src & int_high_src_mask;
168 /* Execute all interrupt handlers */
169 /* Check for timer interrupt */
170 if (irq_src & 0x00000800) {
172 irq_src &= ~0x00000800;
173 // RESET_REG_BITS (INTERRUPT_CAUSE_REGISTER,BIT8);
179 "Other Galileo interrupt received irq_src %x\n",
182 for (count = 0; count < MAX_CAUSE_REG_WIDTH; count++) {
183 if (irq_src & (1 << count)) {
184 if (irq_handlers[INT_CAUSE_MAIN][count].
186 queue_task(&irq_handlers
187 [INT_CAUSE_MAIN][count],
189 mark_bh(IMMEDIATE_BH);
197 GT_WRITE(GT_INTRCAUSE_OFS, 0);
198 GT_WRITE(GT_HINTRCAUSE_OFS, 0);
204 * Future I2O support. We currently attach I2O interrupt handlers to
205 * the Galileo interrupt (int 4) and handle them in do_IRQ.
207 if (isInBoundDoorBellInterruptSet()) {
208 printk(KERN_INFO "I2O doorbell interrupt received.\n");
212 if (isInBoundPostQueueInterruptSet()) {
213 printk(KERN_INFO "I2O Queue interrupt received.\n");
218 * This normally would be outside of the ifdef, but since we're
219 * handling I2O outside of this handler, this printk shows up every
220 * time we get a valid I2O interrupt. So turn this off for now.
224 printk("Spurious Galileo interrupt...\n");
232 * Initializes timer using galileo's built in timer.
236 * This will ignore the standard MIPS timer interrupt handler
237 * that is passed in as *irq (=irq0 in ../kernel/time.c).
238 * We will do our own timer interrupt handling.
240 void gt64240_time_init(void)
242 extern irq_desc_t irq_desc[NR_IRQS];
243 static struct irqaction timer;
245 /* Stop the timer -- we'll use timer #0 */
246 GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0);
248 /* Load timer value for 100 Hz */
249 GT_WRITE(TIMER_COUNTER0, bus_clock / 100);
252 * Create the IRQ structure entry for the timer. Since we're too early
253 * in the boot process to use the "request_irq()" call, we'll hard-code
254 * the values to the correct interrupt line.
256 timer.handler = >64240_p0int_irq;
257 timer.flags = SA_SHIRQ | SA_INTERRUPT;
258 timer.name = "timer";
262 irq_desc[6].action = &timer;
266 /* Clear any pending cause bits */
267 GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
269 /* Enable the interrupt for timer 0 */
270 GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1);
272 /* Enable the timer interrupt for GT-64240 pin P0_INT# */
273 GT_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100);
275 /* Configure and start the timer */
276 GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3);
279 void gt64240_irq_init(void)
284 /* Reset irq handlers pointers to NULL */
285 for (i = 0; i < MAX_CAUSE_REGS; i++) {
286 for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) {
287 irq_handlers[i][j].next = NULL;
288 irq_handlers[i][j].sync = 0;
289 irq_handlers[i][j].routine = NULL;
290 irq_handlers[i][j].data = NULL;