arch/mips/pci/pci_auto.c

   1 /*
   2  * PCI autoconfiguration library
   3  *
   4  * Author: Matt Porter <mporter@mvista.com>
   5  *
   6  * Copyright 2000, 2001, 2002, 2003 MontaVista Software Inc.
   7  * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 /*
  16  * Modified for MIPS by Jun Sun, jsun@mvista.com
  17  *
  18  * . Simplify the interface between pci_auto and the rest: a single function.
  19  * . Assign resources from low address to upper address.
  20  * . change most int to u32.
  21  *
  22  * Further modified to include it as mips generic code, ppopov@mvista.com.
  23  *
  24  * 2001-10-26  Bradley D. LaRonde <brad@ltc.com>
  25  * - Add a top_bus argument to the "early config" functions so that
  26  *   they can set a fake parent bus pointer to convince the underlying
  27  *   pci ops to use type 1 configuration for sub busses.
  28  * - Set bridge base and limit registers correctly.
  29  * - Align io and memory base properly before and after bridge setup.
  30  * - Don't fall through to pci_setup_bars for bridge.
  31  * - Reformat the debug output to look more like lspci's output.
  32  *
  33  * 2003-04-09 Yoichi Yuasa, Alice Hennessy, Jun Sun
  34  * - Add cardbus bridge support, mostly copied from PPC
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/init.h>
  39 #include <linux/types.h>
  40 #include <linux/pci.h>
  41
  42 #include <asm/pci_channel.h>
  43
  44 #define DEBUG
  45 #ifdef  DEBUG
  46 #define DBG(x...)       printk(x)
  47 #else
  48 #define DBG(x...)
  49 #endif
  50
  51 /*
  52  * These functions are used early on before PCI scanning is done
  53  * and all of the pci_dev and pci_bus structures have been created.
  54  */
  55 static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
  56         int top_bus, int busnr, int devfn)
  57 {
  58         static struct pci_dev dev;
  59         static struct pci_bus bus;
  60
  61         dev.bus = &bus;
  62         dev.sysdata = hose;
  63         dev.devfn = devfn;
  64         bus.number = busnr;
  65         bus.ops = hose->pci_ops;
  66
  67         if(busnr != top_bus)
  68                 /* Fake a parent bus structure. */
  69                 bus.parent = &bus;
  70         else
  71                 bus.parent = NULL;
  72
  73         return &dev;
  74 }
  75
  76 #define EARLY_PCI_OP(rw, size, type)                                    \
  77 int early_##rw##_config_##size(struct pci_channel *hose,                \
  78         int top_bus, int bus, int devfn, int offset, type value)        \
  79 {                                                                       \
  80         return pci_##rw##_config_##size(                                \
  81                 fake_pci_dev(hose, top_bus, bus, devfn),                \
  82                 offset, value);                                         \
  83 }
  84
  85 EARLY_PCI_OP(read, byte, u8 *)
  86 EARLY_PCI_OP(read, word, u16 *)
  87 EARLY_PCI_OP(read, dword, u32 *)
  88 EARLY_PCI_OP(write, byte, u8)
  89 EARLY_PCI_OP(write, word, u16)
  90 EARLY_PCI_OP(write, dword, u32)
  91
  92 static struct resource *io_resource_inuse;
  93 static struct resource *mem_resource_inuse;
  94
  95 static u32 pciauto_lower_iospc;
  96 static u32 pciauto_upper_iospc;
  97
  98 static u32 pciauto_lower_memspc;
  99 static u32 pciauto_upper_memspc;
 100
 101 void __init
 102 pciauto_setup_bars(struct pci_channel *hose,
 103                    int top_bus,
 104                    int current_bus,
 105                    int pci_devfn,
 106                    int bar_limit)
 107 {
 108         u32 bar_response, bar_size, bar_value;
 109         u32 bar, addr_mask, bar_nr = 0;
 110         u32 * upper_limit;
 111         u32 * lower_limit;
 112         int found_mem64 = 0;
 113
 114         for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
 115                 /* Tickle the BAR and get the response */
 116                 early_write_config_dword(hose, top_bus,
 117                                          current_bus,
 118                                          pci_devfn,
 119                                          bar,
 120                                          0xffffffff);
 121                 early_read_config_dword(hose, top_bus,
 122                                         current_bus,
 123                                         pci_devfn,
 124                                         bar,
 125                                         &bar_response);
 126
 127                 /* If BAR is not implemented go to the next BAR */
 128                 if (!bar_response)
 129                         continue;
 130
 131                 /*
 132                  * Workaround for a BAR that doesn't use its upper word,
 133                  * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
 134                  * bdl <brad@ltc.com>
 135                  */
 136                 if (!(bar_response & 0xffff0000))
 137                         bar_response |= 0xffff0000;
 138
 139 retry:
 140                 /* Check the BAR type and set our address mask */
 141                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 142                         addr_mask = PCI_BASE_ADDRESS_IO_MASK;
 143                         upper_limit = &pciauto_upper_iospc;
 144                         lower_limit = &pciauto_lower_iospc;
 145                         DBG("        I/O");
 146                 } else {
 147                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 148                             PCI_BASE_ADDRESS_MEM_TYPE_64)
 149                                 found_mem64 = 1;
 150
 151                         addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
 152                         upper_limit = &pciauto_upper_memspc;
 153                         lower_limit = &pciauto_lower_memspc;
 154                         DBG("        Mem");
 155                 }
 156
 157
 158                 /* Calculate requested size */
 159                 bar_size = ~(bar_response & addr_mask) + 1;
 160
 161                 /* Allocate a base address */
 162                 bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
 163
 164                 if ((bar_value + bar_size) > *upper_limit) {
 165                         if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 166                                 if (io_resource_inuse->child) {
 167                                         io_resource_inuse =
 168                                                 io_resource_inuse->child;
 169                                         pciauto_lower_iospc =
 170                                                 io_resource_inuse->start;
 171                                         pciauto_upper_iospc =
 172                                                 io_resource_inuse->end + 1;
 173                                         goto retry;
 174                                 }
 175
 176                         } else {
 177                                 if (mem_resource_inuse->child) {
 178                                         mem_resource_inuse =
 179                                                 mem_resource_inuse->child;
 180                                         pciauto_lower_memspc =
 181                                                 mem_resource_inuse->start;
 182                                         pciauto_upper_memspc =
 183                                                 mem_resource_inuse->end + 1;
 184                                         goto retry;
 185                                 }
 186                         }
 187                         DBG(" unavailable -- skipping\n");
 188                         continue;
 189                 }
 190
 191                 /* Write it out and update our limit */
 192                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 193                                          bar, bar_value);
 194
 195                 *lower_limit = bar_value + bar_size;
 196
 197                 /*
 198                  * If we are a 64-bit decoder then increment to the
 199                  * upper 32 bits of the bar and force it to locate
 200                  * in the lower 4GB of memory.
 201                  */
 202                 if (found_mem64) {
 203                         bar += 4;
 204                         early_write_config_dword(hose, top_bus,
 205                                                  current_bus,
 206                                                  pci_devfn,
 207                                                  bar,
 208                                                  0x00000000);
 209                 }
 210
 211                 DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
 212
 213                 bar_nr++;
 214         }
 215
 216 }
 217
 218 void __init
 219 pciauto_prescan_setup_bridge(struct pci_channel *hose,
 220                              int top_bus,
 221                              int current_bus,
 222                              int pci_devfn,
 223                              int sub_bus)
 224 {
 225         /* Configure bus number registers */
 226         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 227                                 PCI_PRIMARY_BUS, current_bus);
 228         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 229                                 PCI_SECONDARY_BUS, sub_bus + 1);
 230         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 231                                 PCI_SUBORDINATE_BUS, 0xff);
 232
 233         /* Align memory and I/O to 1MB and 4KB boundaries. */
 234         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 235                 & ~(0x100000 - 1);
 236         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 237                 & ~(0x1000 - 1);
 238
 239         /* Set base (lower limit) of address range behind bridge. */
 240         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 241                 PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
 242         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 243                 PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
 244         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 245                 PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
 246
 247         /* We don't support prefetchable memory for now, so disable */
 248         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 249                                 PCI_PREF_MEMORY_BASE, 0);
 250         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 251                                 PCI_PREF_MEMORY_LIMIT, 0);
 252 }
 253
 254 void __init
 255 pciauto_postscan_setup_bridge(struct pci_channel *hose,
 256                               int top_bus,
 257                               int current_bus,
 258                               int pci_devfn,
 259                               int sub_bus)
 260 {
 261         u32 temp;
 262
 263         /*
 264          * [jsun] we always bump up baselines a little, so that if there
 265          * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
 266          * spaces.
 267          */
 268         pciauto_lower_memspc += 1;
 269         pciauto_lower_iospc += 1;
 270
 271         /* Configure bus number registers */
 272         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 273                                 PCI_SUBORDINATE_BUS, sub_bus);
 274
 275         /* Set upper limit of address range behind bridge. */
 276         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 277                 PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
 278         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 279                 PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
 280         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 281                 PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
 282
 283         /* Align memory and I/O to 1MB and 4KB boundaries. */
 284         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 285                 & ~(0x100000 - 1);
 286         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 287                 & ~(0x1000 - 1);
 288
 289         /* Enable memory and I/O accesses, enable bus master */
 290         early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 291                 PCI_COMMAND, &temp);
 292         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 293                 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 294                 | PCI_COMMAND_MASTER);
 295 }
 296
 297 void __init
 298 pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
 299                             int top_bus,
 300                             int current_bus,
 301                             int pci_devfn,
 302                             int sub_bus)
 303 {
 304        /* Configure bus number registers */
 305        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 306                                PCI_PRIMARY_BUS, current_bus);
 307        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 308                                PCI_SECONDARY_BUS, sub_bus + 1);
 309        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 310                                PCI_SUBORDINATE_BUS, 0xff);
 311
 312        /* Align memory and I/O to 4KB and 4 byte boundaries. */
 313        pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
 314                & ~(0x1000 - 1);
 315        pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
 316                & ~(0x4 - 1);
 317
 318        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 319                PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
 320        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 321                PCI_CB_IO_BASE_0, pciauto_lower_iospc);
 322 }
 323
 324 void __init
 325 pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
 326                              int top_bus,
 327                              int current_bus,
 328                              int pci_devfn,
 329                              int sub_bus)
 330 {
 331         u32 temp;
 332
 333         /*
 334          * Configure subordinate bus number.  The PCI subsystem
 335          * bus scan will renumber buses (reserving three additional
 336          * for this PCI<->CardBus bridge for the case where a CardBus
 337          * adapter contains a P2P or CB2CB bridge.
 338          */
 339
 340        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 341                                PCI_SUBORDINATE_BUS, sub_bus);
 342
 343         /*
 344          * Reserve an additional 4MB for mem space and 16KB for
 345          * I/O space.  This should cover any additional space
 346          * requirement of unusual CardBus devices with
 347          * additional bridges that can consume more address space.
 348          *
 349          * Although pcmcia-cs currently will reprogram bridge
 350          * windows, the goal is to add an option to leave them
 351          * alone and use the bridge window ranges as the regions
 352          * that are searched for free resources upon hot-insertion
 353          * of a device.  This will allow a PCI<->CardBus bridge
 354          * configured by this routine to happily live behind a
 355          * P2P bridge in a system.
 356          */
 357         pciauto_lower_memspc += 0x00400000;
 358         pciauto_lower_iospc += 0x00004000;
 359
 360         /* Align memory and I/O to 4KB and 4 byte boundaries. */
 361         pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
 362                                 & ~(0x1000 - 1);
 363         pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
 364                                 & ~(0x4 - 1);
 365         /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 366         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 367                         PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
 368         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 369                         PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);
 370
 371         /* Enable memory and I/O accesses, enable bus master */
 372         early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 373                         PCI_COMMAND, &temp);
 374         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 375                 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 376                 | PCI_COMMAND_MASTER);
 377 }
 378
 379 #define      PCIAUTO_IDE_MODE_MASK           0x05
 380
 381 int __init
 382 pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
 383 {
 384         int sub_bus;
 385         u32 pci_devfn, pci_class, cmdstat, found_multi=0;
 386         unsigned short vid, did;
 387         unsigned char header_type;
 388         int devfn_start = 0;
 389         int devfn_stop = 0xff;
 390
 391         sub_bus = current_bus;
 392
 393         if (hose->first_devfn)
 394                 devfn_start = hose->first_devfn;
 395         if (hose->last_devfn)
 396                 devfn_stop = hose->last_devfn;
 397
 398         for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
 399
 400                 if (PCI_FUNC(pci_devfn) && !found_multi)
 401                         continue;
 402
 403                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 404                                        PCI_VENDOR_ID, &vid);
 405
 406                 if (vid == 0xffff) continue;
 407
 408                 early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
 409                                        PCI_HEADER_TYPE, &header_type);
 410
 411                 if (!PCI_FUNC(pci_devfn))
 412                         found_multi = header_type & 0x80;
 413
 414                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 415                                        PCI_DEVICE_ID, &did);
 416
 417                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 418                                         PCI_CLASS_REVISION, &pci_class);
 419
 420                 DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
 421                         current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
 422                         pci_class >> 16, vid, did);
 423                 if (pci_class & 0xff)
 424                         DBG(" (rev %.2x)", pci_class & 0xff);
 425                 DBG("\n");
 426
 427                 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
 428                         DBG("        Bridge: primary=%.2x, secondary=%.2x\n",
 429                                 current_bus, sub_bus + 1);
 430                         pciauto_setup_bars(hose, top_bus, current_bus,
 431                                         pci_devfn, PCI_BASE_ADDRESS_1);
 432                         pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
 433                                                      pci_devfn, sub_bus);
 434                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 435                                 sub_bus + 1,
 436                                 pciauto_lower_iospc, pciauto_lower_memspc);
 437                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 438                         DBG("Back to bus %.2x\n", current_bus);
 439                         pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
 440                                                       pci_devfn, sub_bus);
 441                         continue;
 442                 } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
 443                         DBG("  CARDBUS  Bridge: primary=%.2x, secondary=%.2x\n",
 444                                 current_bus, sub_bus + 1);
 445                         DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
 446                         /* Place CardBus Socket/ExCA registers */
 447                         pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
 448
 449                         pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
 450                                         current_bus, pci_devfn, sub_bus);
 451
 452                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 453                                 sub_bus + 1,
 454                                 pciauto_lower_iospc, pciauto_lower_memspc);
 455                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 456                         DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
 457                         pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
 458                                         current_bus, pci_devfn, sub_bus);
 459                         continue;
 460                 } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
 461
 462                         unsigned char prg_iface;
 463
 464                         early_read_config_byte(hose, top_bus, current_bus,
 465                                 pci_devfn, PCI_CLASS_PROG, &prg_iface);
 466                         if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
 467                                 DBG("Skipping legacy mode IDE controller\n");
 468                                 continue;
 469                         }
 470                 }
 471
 472                 /*
 473                  * Found a peripheral, enable some standard
 474                  * settings
 475                  */
 476                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 477                                         PCI_COMMAND, &cmdstat);
 478                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 479                                          PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
 480                                          PCI_COMMAND_MEMORY |
 481                                          PCI_COMMAND_MASTER);
 482                 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 483                                         PCI_LATENCY_TIMER, 0x80);
 484
 485                 /* Allocate PCI I/O and/or memory space */
 486                 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
 487         }
 488         return sub_bus;
 489 }
 490
 491 int __init
 492 pciauto_assign_resources(int busno, struct pci_channel *hose)
 493 {
 494         /* setup resource limits */
 495         io_resource_inuse = hose->io_resource;
 496         mem_resource_inuse = hose->mem_resource;
 497
 498         pciauto_lower_iospc = io_resource_inuse->start;
 499         pciauto_upper_iospc = io_resource_inuse->end + 1;
 500         pciauto_lower_memspc = mem_resource_inuse->start;
 501         pciauto_upper_memspc = mem_resource_inuse->end + 1;
 502         DBG("Autoconfig PCI channel 0x%p\n", hose);
 503         DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
 504                 busno, pciauto_lower_iospc, pciauto_upper_iospc,
 505                 pciauto_lower_memspc, pciauto_upper_memspc);
 506
 507         return pciauto_bus_scan(hose, busno, busno);
 508 }