2 * BK Id: SCCS/s.fcc_enet.c 1.15 05/28/02 11:49:26 trini
5 * Fast Ethernet Controller (FCC) driver for Motorola MPC8260.
6 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
8 * This version of the driver is a combination of the 8xx fec and
9 * 8260 SCC Ethernet drivers. This version has some additional
10 * configuration options, which should probably be moved out of
11 * here. This driver currently works for the EST SBC8260,
12 * SBS Diablo/BCM, Embedded Planet RPX6, TQM8260, and others.
14 * Right now, I am very watseful with the buffers. I allocate memory
15 * pages and then divide them into 2K frame buffers. This way I know I
16 * have buffers large enough to hold one frame within one buffer descriptor.
17 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
18 * will be much more memory efficient and will easily handle lots of
19 * small packets. Since this is a cache coherent processor and CPM,
20 * I could also preallocate SKB's and use them directly on the interface.
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/string.h>
28 #include <linux/ptrace.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/pci.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/spinlock.h>
41 #include <asm/immap_8260.h>
42 #include <asm/pgtable.h>
43 #include <asm/mpc8260.h>
45 #include <asm/bitops.h>
46 #include <asm/uaccess.h>
47 #include <asm/cpm_8260.h>
49 /* The transmitter timeout
51 #define TX_TIMEOUT (2*HZ)
53 #ifdef CONFIG_USE_MDIO
54 /* Forward declarations of some structures to support different PHYs */
58 void (*funct)(uint mii_reg, struct net_device *dev);
65 const phy_cmd_t *config;
66 const phy_cmd_t *startup;
67 const phy_cmd_t *ack_int;
68 const phy_cmd_t *shutdown;
71 /* Register definitions for the PHY. */
73 #define MII_REG_CR 0 /* Control Register */
74 #define MII_REG_SR 1 /* Status Register */
75 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
76 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
77 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
78 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
79 #define MII_REG_ANER 6 /* A-N Expansion Register */
80 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
81 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
83 /* values for phy_status */
85 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
86 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
87 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
88 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
89 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
90 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
91 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
93 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
94 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
95 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
96 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
97 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
98 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
99 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
100 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
101 #endif /* CONFIG_USE_MDIO */
103 /* The number of Tx and Rx buffers. These are allocated from the page
104 * pool. The code may assume these are power of two, so it is best
105 * to keep them that size.
106 * We don't need to allocate pages for the transmitter. We just use
107 * the skbuffer directly.
109 #define FCC_ENET_RX_PAGES 16
110 #define FCC_ENET_RX_FRSIZE 2048
111 #define FCC_ENET_RX_FRPPG (PAGE_SIZE / FCC_ENET_RX_FRSIZE)
112 #define RX_RING_SIZE (FCC_ENET_RX_FRPPG * FCC_ENET_RX_PAGES)
113 #define TX_RING_SIZE 16 /* Must be power of two */
114 #define TX_RING_MOD_MASK 15 /* for this to work */
116 /* The FCC stores dest/src/type, data, and checksum for receive packets.
118 #define PKT_MAXBUF_SIZE 1518
119 #define PKT_MINBUF_SIZE 64
121 /* Maximum input DMA size. Must be a should(?) be a multiple of 4.
123 #define PKT_MAXDMA_SIZE 1520
125 /* Maximum input buffer size. Must be a multiple of 32.
127 #define PKT_MAXBLR_SIZE 1536
129 static int fcc_enet_open(struct net_device *dev);
130 static int fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
131 static int fcc_enet_rx(struct net_device *dev);
132 static void fcc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs);
133 static int fcc_enet_close(struct net_device *dev);
134 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev);
135 static void set_multicast_list(struct net_device *dev);
136 static void fcc_restart(struct net_device *dev, int duplex);
137 static int fcc_enet_set_mac_address(struct net_device *dev, void *addr);
139 /* These will be configurable for the FCC choice.
140 * Multiple ports can be configured. There is little choice among the
141 * I/O pins to the PHY, except the clocks. We will need some board
142 * dependent clock selection.
143 * Why in the hell did I put these inside #ifdef's? I dunno, maybe to
144 * help show what pins are used for each device.
147 /* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
148 * but there is little variation among the choices.
150 #define PA1_COL ((uint)0x00000001)
151 #define PA1_CRS ((uint)0x00000002)
152 #define PA1_TXER ((uint)0x00000004)
153 #define PA1_TXEN ((uint)0x00000008)
154 #define PA1_RXDV ((uint)0x00000010)
155 #define PA1_RXER ((uint)0x00000020)
156 #define PA1_TXDAT ((uint)0x00003c00)
157 #define PA1_RXDAT ((uint)0x0003c000)
158 #define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
159 #define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
161 #define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
162 #define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
164 /* CLK12 is receive, CLK11 is transmit. These are board specific.
166 #define PC_F1RXCLK ((uint)0x00000800)
167 #define PC_F1TXCLK ((uint)0x00000400)
168 #define CMX1_CLK_ROUTE ((uint)0x3e000000)
169 #define CMX1_CLK_MASK ((uint)0xff000000)
171 /* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
172 * but there is little variation among the choices.
174 #define PB2_TXER ((uint)0x00000001)
175 #define PB2_RXDV ((uint)0x00000002)
176 #define PB2_TXEN ((uint)0x00000004)
177 #define PB2_RXER ((uint)0x00000008)
178 #define PB2_COL ((uint)0x00000010)
179 #define PB2_CRS ((uint)0x00000020)
180 #define PB2_TXDAT ((uint)0x000003c0)
181 #define PB2_RXDAT ((uint)0x00003c00)
182 #define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
183 PB2_RXER | PB2_RXDV | PB2_TXER)
184 #define PB2_PSORB1 (PB2_TXEN)
185 #define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
186 #define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
188 /* CLK13 is receive, CLK14 is transmit. These are board dependent.
190 #define PC_F2RXCLK ((uint)0x00001000)
191 #define PC_F2TXCLK ((uint)0x00002000)
192 #define CMX2_CLK_ROUTE ((uint)0x00250000)
193 #define CMX2_CLK_MASK ((uint)0x00ff0000)
195 /* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
196 * but there is little variation among the choices.
198 #define PB3_RXDV ((uint)0x00004000)
199 #define PB3_RXER ((uint)0x00008000)
200 #define PB3_TXER ((uint)0x00010000)
201 #define PB3_TXEN ((uint)0x00020000)
202 #define PB3_COL ((uint)0x00040000)
203 #define PB3_CRS ((uint)0x00080000)
204 #define PB3_TXDAT ((uint)0x0f000000)
205 #define PB3_RXDAT ((uint)0x00f00000)
206 #define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
207 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
208 #define PB3_PSORB1 (0)
209 #define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
210 #define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
212 /* CLK15 is receive, CLK16 is transmit. These are board dependent.
214 #define PC_F3RXCLK ((uint)0x00004000)
215 #define PC_F3TXCLK ((uint)0x00008000)
216 #define CMX3_CLK_ROUTE ((uint)0x00003700)
217 #define CMX3_CLK_MASK ((uint)0x0000ff00)
219 /* MII status/control serial interface.
221 #ifdef CONFIG_TQM8260
222 /* TQM8260 has MDIO and MDCK on PC30 and PC31 respectively */
223 #define PC_MDIO ((uint)0x00000002)
224 #define PC_MDCK ((uint)0x00000001)
226 #define PC_MDIO ((uint)0x00000004)
227 #define PC_MDCK ((uint)0x00000020)
230 /* A table of information for supporting FCCs. This does two things.
231 * First, we know how many FCCs we have and they are always externally
232 * numbered from zero. Second, it holds control register and I/O
233 * information that could be different among board designs.
235 typedef struct fcc_info {
248 static fcc_info_t fcc_ports[] = {
249 #ifdef CONFIG_FCC1_ENET
250 { 0, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, PROFF_FCC1, SIU_INT_FCC1,
251 (PC_F1RXCLK | PC_F1TXCLK), CMX1_CLK_ROUTE, CMX1_CLK_MASK,
252 # if defined(CONFIG_TQM8260)
255 0x00000004, 0x00000100 },
258 #ifdef CONFIG_FCC2_ENET
259 { 1, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, PROFF_FCC2, SIU_INT_FCC2,
260 (PC_F2RXCLK | PC_F2TXCLK), CMX2_CLK_ROUTE, CMX2_CLK_MASK,
261 # if defined(CONFIG_TQM8260)
263 # elif defined(CONFIG_EST8260) || defined(CONFIG_ADS8260)
264 0x00400000, 0x00200000 },
266 0x00000002, 0x00000080 },
269 #ifdef CONFIG_FCC3_ENET
270 { 2, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, PROFF_FCC3, SIU_INT_FCC3,
271 (PC_F3RXCLK | PC_F3TXCLK), CMX3_CLK_ROUTE, CMX3_CLK_MASK,
272 # if defined(CONFIG_TQM8260)
275 0x00000001, 0x00000040 },
280 /* The FCC buffer descriptors track the ring buffers. The rx_bd_base and
281 * tx_bd_base always point to the base of the buffer descriptors. The
282 * cur_rx and cur_tx point to the currently available buffer.
283 * The dirty_tx tracks the current buffer that is being sent by the
284 * controller. The cur_tx and dirty_tx are equal under both completely
285 * empty and completely full conditions. The empty/ready indicator in
286 * the buffer descriptor determines the actual condition.
288 struct fcc_enet_private {
289 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
290 struct sk_buff* tx_skbuff[TX_RING_SIZE];
294 /* CPM dual port RAM relative addresses.
296 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
298 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
299 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
300 volatile fcc_t *fccp;
301 volatile fcc_enet_t *ep;
302 struct net_device_stats stats;
306 #ifdef CONFIG_USE_MDIO
311 struct tq_struct phy_task;
316 #endif /* CONFIG_USE_MDIO */
325 static void init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
326 volatile immap_t *immap);
327 static void init_fcc_startup(fcc_info_t *fip, struct net_device *dev);
328 static void init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
329 volatile immap_t *immap);
330 static void init_fcc_param(fcc_info_t *fip, struct net_device *dev,
331 volatile immap_t *immap);
333 #ifdef CONFIG_USE_MDIO
334 static int mii_queue(struct net_device *dev, int request, void (*func)(uint, struct net_device *));
335 static uint mii_send_receive(fcc_info_t *fip, uint cmd);
337 static void fcc_stop(struct net_device *dev);
339 /* Make MII read/write commands for the FCC.
341 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
342 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
345 #endif /* CONFIG_USE_MDIO */
349 fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
351 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
355 /* Link is down or autonegotiation is in progress. */
359 /* Fill in a Tx ring entry */
362 #ifndef final_version
363 if (bdp->cbd_sc & BD_ENET_TX_READY) {
364 /* Ooops. All transmit buffers are full. Bail out.
365 * This should not happen, since cep->tx_full should be set.
367 printk("%s: tx queue full!.\n", dev->name);
372 /* Clear all of the status flags. */
373 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
375 /* If the frame is short, tell CPM to pad it. */
376 if (skb->len <= ETH_ZLEN)
377 bdp->cbd_sc |= BD_ENET_TX_PAD;
379 bdp->cbd_sc &= ~BD_ENET_TX_PAD;
381 /* Set buffer length and buffer pointer. */
382 bdp->cbd_datlen = skb->len;
383 bdp->cbd_bufaddr = __pa(skb->data);
385 /* Save skb pointer. */
386 cep->tx_skbuff[cep->skb_cur] = skb;
388 cep->stats.tx_bytes += skb->len;
389 cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK;
391 spin_lock_irq(&cep->lock);
393 /* Send it on its way. Tell CPM its ready, interrupt when done,
394 * its the last BD of the frame, and to put the CRC on the end.
396 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC);
399 /* Errata says don't do this. */
400 cep->fccp->fcc_ftodr = 0x8000;
402 dev->trans_start = jiffies;
404 /* If this was the last BD in the ring, start at the beginning again. */
405 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
406 bdp = cep->tx_bd_base;
410 if (bdp->cbd_sc & BD_ENET_TX_READY) {
411 netif_stop_queue(dev);
415 cep->cur_tx = (cbd_t *)bdp;
417 spin_unlock_irq(&cep->lock);
424 fcc_enet_timeout(struct net_device *dev)
426 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
428 printk("%s: transmit timed out.\n", dev->name);
429 cep->stats.tx_errors++;
430 #ifndef final_version
434 printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n",
435 cep->cur_tx, cep->tx_full ? " (full)" : "",
437 bdp = cep->tx_bd_base;
438 printk(" Tx @base %p :\n", bdp);
439 for (i = 0 ; i < TX_RING_SIZE; i++, bdp++)
440 printk("%04x %04x %08x\n",
444 bdp = cep->rx_bd_base;
445 printk(" Rx @base %p :\n", bdp);
446 for (i = 0 ; i < RX_RING_SIZE; i++, bdp++)
447 printk("%04x %04x %08x\n",
454 netif_wake_queue(dev);
457 /* The interrupt handler. */
459 fcc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
461 struct net_device *dev = dev_id;
462 volatile struct fcc_enet_private *cep;
467 cep = (struct fcc_enet_private *)dev->priv;
469 /* Get the interrupt events that caused us to be here.
471 int_events = cep->fccp->fcc_fcce;
472 cep->fccp->fcc_fcce = int_events;
475 /* Handle receive event in its own function.
477 if (int_events & FCC_ENET_RXF)
480 /* Check for a transmit error. The manual is a little unclear
481 * about this, so the debug code until I get it figured out. It
482 * appears that if TXE is set, then TXB is not set. However,
483 * if carrier sense is lost during frame transmission, the TXE
484 * bit is set, "and continues the buffer transmission normally."
485 * I don't know if "normally" implies TXB is set when the buffer
486 * descriptor is closed.....trial and error :-).
489 /* Transmit OK, or non-fatal error. Update the buffer descriptors.
491 if (int_events & (FCC_ENET_TXE | FCC_ENET_TXB)) {
492 spin_lock(&cep->lock);
494 while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) {
495 if ((bdp==cep->cur_tx) && (cep->tx_full == 0))
498 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
499 cep->stats.tx_heartbeat_errors++;
500 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
501 cep->stats.tx_window_errors++;
502 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
503 cep->stats.tx_aborted_errors++;
504 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
505 cep->stats.tx_fifo_errors++;
506 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
507 cep->stats.tx_carrier_errors++;
510 /* No heartbeat or Lost carrier are not really bad errors.
511 * The others require a restart transmit command.
514 (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) {
516 cep->stats.tx_errors++;
519 cep->stats.tx_packets++;
521 /* Deferred means some collisions occurred during transmit,
522 * but we eventually sent the packet OK.
524 if (bdp->cbd_sc & BD_ENET_TX_DEF)
525 cep->stats.collisions++;
527 /* Free the sk buffer associated with this last transmit. */
528 dev_kfree_skb_irq(cep->tx_skbuff[cep->skb_dirty]);
529 cep->skb_dirty = (cep->skb_dirty + 1) & TX_RING_MOD_MASK;
531 /* Update pointer to next buffer descriptor to be transmitted. */
532 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
533 bdp = cep->tx_bd_base;
537 /* I don't know if we can be held off from processing these
538 * interrupts for more than one frame time. I really hope
539 * not. In such a case, we would now want to check the
540 * currently available BD (cur_tx) and determine if any
541 * buffers between the dirty_tx and cur_tx have also been
542 * sent. We would want to process anything in between that
543 * does not have BD_ENET_TX_READY set.
546 /* Since we have freed up a buffer, the ring is no longer
551 if (netif_queue_stopped(dev)) {
552 netif_wake_queue(dev);
556 cep->dirty_tx = (cbd_t *)bdp;
560 volatile cpm8260_t *cp;
562 /* Some transmit errors cause the transmitter to shut
563 * down. We now issue a restart transmit. Since the
564 * errors close the BD and update the pointers, the restart
565 * _should_ pick up without having to reset any of our
566 * pointers either. Also, To workaround 8260 device erratum
567 * CPM37, we must disable and then re-enable the transmitter
568 * following a Late Collision, Underrun, or Retry Limit error.
570 cep->fccp->fcc_gfmr &= ~FCC_GFMR_ENT;
571 udelay(10); /* wait a few microseconds just on principle */
572 cep->fccp->fcc_gfmr |= FCC_GFMR_ENT;
576 mk_cr_cmd(cep->fip->fc_cpmpage, cep->fip->fc_cpmblock,
577 0x0c, CPM_CR_RESTART_TX) | CPM_CR_FLG;
578 while (cp->cp_cpcr & CPM_CR_FLG);
580 spin_unlock(&cep->lock);
583 /* Check for receive busy, i.e. packets coming but no place to
586 if (int_events & FCC_ENET_BSY) {
587 cep->stats.rx_dropped++;
592 /* During a receive, the cur_rx points to the current incoming buffer.
593 * When we update through the ring, if the next incoming buffer has
594 * not been given to the system, we just set the empty indicator,
595 * effectively tossing the packet.
598 fcc_enet_rx(struct net_device *dev)
600 struct fcc_enet_private *cep;
605 cep = (struct fcc_enet_private *)dev->priv;
607 /* First, grab all of the stats for the incoming packet.
608 * These get messed up if we get called due to a busy condition.
613 if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
616 #ifndef final_version
617 /* Since we have allocated space to hold a complete frame, both
618 * the first and last indicators should be set.
620 if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) !=
621 (BD_ENET_RX_FIRST | BD_ENET_RX_LAST))
622 printk("CPM ENET: rcv is not first+last\n");
625 /* Frame too long or too short. */
626 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH))
627 cep->stats.rx_length_errors++;
628 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
629 cep->stats.rx_frame_errors++;
630 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
631 cep->stats.rx_crc_errors++;
632 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
633 cep->stats.rx_crc_errors++;
634 if (bdp->cbd_sc & BD_ENET_RX_CL) /* Late Collision */
635 cep->stats.rx_frame_errors++;
638 (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | BD_ENET_RX_CR
639 | BD_ENET_RX_OV | BD_ENET_RX_CL)))
641 /* Process the incoming frame. */
642 cep->stats.rx_packets++;
644 /* Remove the FCS from the packet length. */
645 pkt_len = bdp->cbd_datlen - 4;
646 cep->stats.rx_bytes += pkt_len;
648 /* This does 16 byte alignment, much more than we need. */
649 skb = dev_alloc_skb(pkt_len);
652 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
653 cep->stats.rx_dropped++;
657 skb_put(skb,pkt_len); /* Make room */
658 eth_copy_and_sum(skb,
659 (unsigned char *)__va(bdp->cbd_bufaddr),
661 skb->protocol=eth_type_trans(skb,dev);
666 /* Clear the status flags for this buffer. */
667 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
669 /* Mark the buffer empty. */
670 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
672 /* Update BD pointer to next entry. */
673 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
674 bdp = cep->rx_bd_base;
679 cep->cur_rx = (cbd_t *)bdp;
685 fcc_enet_close(struct net_device *dev)
687 /* Don't know what to do yet. */
688 netif_stop_queue(dev);
693 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev)
695 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
700 #ifdef CONFIG_USE_MDIO
702 /* NOTE: Most of the following comes from the FEC driver for 860. The
703 * overall structure of MII code has been retained (as it's proved stable
704 * and well-tested), but actual transfer requests are processed "at once"
705 * instead of being queued (there's no interrupt-driven MII transfer
706 * mechanism, one has to toggle the data/clock bits manually).
709 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
711 struct fcc_enet_private *fep;
714 /* Add PHY address to register command. */
716 regval |= fep->phy_addr << 23;
720 tmp = mii_send_receive(fep->fip, regval);
727 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
734 for(k = 0; (c+k)->mii_data != mk_mii_end; k++)
735 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
738 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
740 volatile struct fcc_enet_private *fep = dev->priv;
741 uint s = fep->phy_status;
743 s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
745 if (mii_reg & 0x0004)
747 if (mii_reg & 0x0010)
749 if (mii_reg & 0x0020)
753 fep->link = (s & PHY_STAT_LINK) ? 1 : 0;
756 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
758 volatile struct fcc_enet_private *fep = dev->priv;
759 uint s = fep->phy_status;
761 s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP);
763 if (mii_reg & 0x1000)
765 if (mii_reg & 0x4000)
771 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
773 volatile struct fcc_enet_private *fep = dev->priv;
774 uint s = fep->phy_status;
776 s &= ~(PHY_CONF_SPMASK);
778 if (mii_reg & 0x0020)
780 if (mii_reg & 0x0040)
782 if (mii_reg & 0x0080)
783 s |= PHY_CONF_100HDX;
784 if (mii_reg & 0x00100)
785 s |= PHY_CONF_100FDX;
789 /* ------------------------------------------------------------------------- */
790 /* The Level one LXT970 is used by many boards */
792 #ifdef CONFIG_FCC_LXT970
794 #define MII_LXT970_MIRROR 16 /* Mirror register */
795 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
796 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
797 #define MII_LXT970_CONFIG 19 /* Configuration Register */
798 #define MII_LXT970_CSR 20 /* Chip Status Register */
800 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
802 volatile struct fcc_enet_private *fep = dev->priv;
803 uint s = fep->phy_status;
805 s &= ~(PHY_STAT_SPMASK);
807 if (mii_reg & 0x0800) {
808 if (mii_reg & 0x1000)
809 s |= PHY_STAT_100FDX;
811 s |= PHY_STAT_100HDX;
813 if (mii_reg & 0x1000)
822 static phy_info_t phy_info_lxt970 = {
826 (const phy_cmd_t []) { /* config */
828 // { mk_mii_write(MII_REG_ANAR, 0x0021), NULL },
830 /* Set default operation of 100-TX....for some reason
831 * some of these bits are set on power up, which is wrong.
833 { mk_mii_write(MII_LXT970_CONFIG, 0), NULL },
835 { mk_mii_read(MII_REG_CR), mii_parse_cr },
836 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
839 (const phy_cmd_t []) { /* startup - enable interrupts */
840 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
841 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
844 (const phy_cmd_t []) { /* ack_int */
845 /* read SR and ISR to acknowledge */
847 { mk_mii_read(MII_REG_SR), mii_parse_sr },
848 { mk_mii_read(MII_LXT970_ISR), NULL },
850 /* find out the current status */
852 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
855 (const phy_cmd_t []) { /* shutdown - disable interrupts */
856 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
861 #endif /* CONFIG_FEC_LXT970 */
863 /* ------------------------------------------------------------------------- */
864 /* The Level one LXT971 is used on some of my custom boards */
866 #ifdef CONFIG_FCC_LXT971
868 /* register definitions for the 971 */
870 #define MII_LXT971_PCR 16 /* Port Control Register */
871 #define MII_LXT971_SR2 17 /* Status Register 2 */
872 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
873 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
874 #define MII_LXT971_LCR 20 /* LED Control Register */
875 #define MII_LXT971_TCR 30 /* Transmit Control Register */
878 * I had some nice ideas of running the MDIO faster...
879 * The 971 should support 8MHz and I tried it, but things acted really
880 * weird, so 2.5 MHz ought to be enough for anyone...
883 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
885 volatile struct fcc_enet_private *fep = dev->priv;
886 uint s = fep->phy_status;
888 s &= ~(PHY_STAT_SPMASK);
890 if (mii_reg & 0x4000) {
891 if (mii_reg & 0x0200)
892 s |= PHY_STAT_100FDX;
894 s |= PHY_STAT_100HDX;
896 if (mii_reg & 0x0200)
901 if (mii_reg & 0x0008)
907 static phy_info_t phy_info_lxt971 = {
911 (const phy_cmd_t []) { /* config */
912 // { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */
913 { mk_mii_read(MII_REG_CR), mii_parse_cr },
914 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
917 (const phy_cmd_t []) { /* startup - enable interrupts */
918 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
919 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
921 /* Somehow does the 971 tell me that the link is down
922 * the first read after power-up.
923 * read here to get a valid value in ack_int */
925 { mk_mii_read(MII_REG_SR), mii_parse_sr },
928 (const phy_cmd_t []) { /* ack_int */
929 /* find out the current status */
931 { mk_mii_read(MII_REG_SR), mii_parse_sr },
932 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
934 /* we only need to read ISR to acknowledge */
936 { mk_mii_read(MII_LXT971_ISR), NULL },
939 (const phy_cmd_t []) { /* shutdown - disable interrupts */
940 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
945 #endif /* CONFIG_FEC_LXT970 */
948 /* ------------------------------------------------------------------------- */
949 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
951 #ifdef CONFIG_FCC_QS6612
953 /* register definitions */
955 #define MII_QS6612_MCR 17 /* Mode Control Register */
956 #define MII_QS6612_FTR 27 /* Factory Test Register */
957 #define MII_QS6612_MCO 28 /* Misc. Control Register */
958 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
959 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
960 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
962 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
964 volatile struct fcc_enet_private *fep = dev->priv;
965 uint s = fep->phy_status;
967 s &= ~(PHY_STAT_SPMASK);
969 switch((mii_reg >> 2) & 7) {
970 case 1: s |= PHY_STAT_10HDX; break;
971 case 2: s |= PHY_STAT_100HDX; break;
972 case 5: s |= PHY_STAT_10FDX; break;
973 case 6: s |= PHY_STAT_100FDX; break;
979 static phy_info_t phy_info_qs6612 = {
983 (const phy_cmd_t []) { /* config */
984 // { mk_mii_write(MII_REG_ANAR, 0x061), NULL }, /* 10 Mbps */
986 /* The PHY powers up isolated on the RPX,
987 * so send a command to allow operation.
990 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
992 /* parse cr and anar to get some info */
994 { mk_mii_read(MII_REG_CR), mii_parse_cr },
995 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
998 (const phy_cmd_t []) { /* startup - enable interrupts */
999 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1000 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1003 (const phy_cmd_t []) { /* ack_int */
1005 /* we need to read ISR, SR and ANER to acknowledge */
1007 { mk_mii_read(MII_QS6612_ISR), NULL },
1008 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1009 { mk_mii_read(MII_REG_ANER), NULL },
1011 /* read pcr to get info */
1013 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1016 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1017 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1023 #endif /* CONFIG_FEC_QS6612 */
1026 /* ------------------------------------------------------------------------- */
1027 /* The Davicom DM9131 is used on the HYMOD board */
1029 #ifdef CONFIG_FCC_DM9131
1031 /* register definitions */
1033 #define MII_DM9131_ACR 16 /* Aux. Config Register */
1034 #define MII_DM9131_ACSR 17 /* Aux. Config/Status Register */
1035 #define MII_DM9131_10TCSR 18 /* 10BaseT Config/Status Reg. */
1036 #define MII_DM9131_INTR 21 /* Interrupt Register */
1037 #define MII_DM9131_RECR 22 /* Receive Error Counter Reg. */
1038 #define MII_DM9131_DISCR 23 /* Disconnect Counter Register */
1040 static void mii_parse_dm9131_acsr(uint mii_reg, struct net_device *dev)
1042 volatile struct fcc_enet_private *fep = dev->priv;
1043 uint s = fep->phy_status;
1045 s &= ~(PHY_STAT_SPMASK);
1047 switch ((mii_reg >> 12) & 0xf) {
1048 case 1: s |= PHY_STAT_10HDX; break;
1049 case 2: s |= PHY_STAT_10FDX; break;
1050 case 4: s |= PHY_STAT_100HDX; break;
1051 case 8: s |= PHY_STAT_100FDX; break;
1054 fep->phy_status = s;
1057 static phy_info_t phy_info_dm9131 = {
1061 (const phy_cmd_t []) { /* config */
1062 /* parse cr and anar to get some info */
1063 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1064 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1067 (const phy_cmd_t []) { /* startup - enable interrupts */
1068 { mk_mii_write(MII_DM9131_INTR, 0x0002), NULL },
1069 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1072 (const phy_cmd_t []) { /* ack_int */
1074 /* we need to read INTR, SR and ANER to acknowledge */
1076 { mk_mii_read(MII_DM9131_INTR), NULL },
1077 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1078 { mk_mii_read(MII_REG_ANER), NULL },
1080 /* read acsr to get info */
1082 { mk_mii_read(MII_DM9131_ACSR), mii_parse_dm9131_acsr },
1085 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1086 { mk_mii_write(MII_DM9131_INTR, 0x0f00), NULL },
1092 #endif /* CONFIG_FEC_DM9131 */
1095 static phy_info_t *phy_info[] = {
1097 #ifdef CONFIG_FCC_LXT970
1099 #endif /* CONFIG_FEC_LXT970 */
1101 #ifdef CONFIG_FCC_LXT971
1103 #endif /* CONFIG_FEC_LXT971 */
1105 #ifdef CONFIG_FCC_QS6612
1107 #endif /* CONFIG_FEC_QS6612 */
1109 #ifdef CONFIG_FCC_DM9131
1111 #endif /* CONFIG_FEC_DM9131 */
1116 static void mii_display_status(struct net_device *dev)
1118 volatile struct fcc_enet_private *fep = dev->priv;
1119 uint s = fep->phy_status;
1121 if (!fep->link && !fep->old_link) {
1122 /* Link is still down - don't print anything */
1126 printk("%s: status: ", dev->name);
1129 printk("link down");
1133 switch(s & PHY_STAT_SPMASK) {
1134 case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break;
1135 case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break;
1136 case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break;
1137 case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break;
1139 printk(", Unknown speed/duplex");
1142 if (s & PHY_STAT_ANC)
1143 printk(", auto-negotiation complete");
1146 if (s & PHY_STAT_FAULT)
1147 printk(", remote fault");
1152 static void mii_display_config(struct net_device *dev)
1154 volatile struct fcc_enet_private *fep = dev->priv;
1155 uint s = fep->phy_status;
1157 printk("%s: config: auto-negotiation ", dev->name);
1159 if (s & PHY_CONF_ANE)
1164 if (s & PHY_CONF_100FDX)
1166 if (s & PHY_CONF_100HDX)
1168 if (s & PHY_CONF_10FDX)
1170 if (s & PHY_CONF_10HDX)
1172 if (!(s & PHY_CONF_SPMASK))
1173 printk(", No speed/duplex selected?");
1175 if (s & PHY_CONF_LOOP)
1176 printk(", loopback enabled");
1180 fep->sequence_done = 1;
1183 static void mii_relink(struct net_device *dev)
1185 struct fcc_enet_private *fep = dev->priv;
1188 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1189 mii_display_status(dev);
1190 fep->old_link = fep->link;
1195 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1197 fcc_restart(dev, duplex);
1203 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1205 struct fcc_enet_private *fep = dev->priv;
1207 fep->phy_task.routine = (void *)mii_relink;
1208 fep->phy_task.data = dev;
1209 schedule_task(&fep->phy_task);
1212 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1214 struct fcc_enet_private *fep = dev->priv;
1216 fep->phy_task.routine = (void *)mii_display_config;
1217 fep->phy_task.data = dev;
1218 schedule_task(&fep->phy_task);
1223 phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_REG_CR), mii_queue_relink },
1225 phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_REG_CR), mii_queue_config },
1229 /* Read remainder of PHY ID.
1232 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1234 struct fcc_enet_private *fep;
1238 fep->phy_id |= (mii_reg & 0xffff);
1240 for(i = 0; phy_info[i]; i++)
1241 if(phy_info[i]->id == (fep->phy_id >> 4))
1245 panic("%s: PHY id 0x%08x is not supported!\n",
1246 dev->name, fep->phy_id);
1248 fep->phy = phy_info[i];
1250 printk("%s: Phy @ 0x%x, type %s (0x%08x)\n",
1251 dev->name, fep->phy_addr, fep->phy->name, fep->phy_id);
1254 /* Scan all of the MII PHY addresses looking for someone to respond
1255 * with a valid ID. This usually happens quickly.
1258 mii_discover_phy(uint mii_reg, struct net_device *dev)
1260 struct fcc_enet_private *fep;
1265 if ((phytype = (mii_reg & 0xfff)) != 0xfff) {
1267 /* Got first part of ID, now get remainder. */
1268 fep->phy_id = phytype << 16;
1269 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), mii_discover_phy3);
1272 if (fep->phy_addr < 32) {
1273 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1276 printk("fec: No PHY device found.\n");
1281 /* This interrupt occurs when the PHY detects a link change. */
1283 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
1285 struct net_device *dev = dev_id;
1286 struct fcc_enet_private *fep = dev->priv;
1288 mii_do_cmd(dev, fep->phy->ack_int);
1289 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1292 #endif /* CONFIG_USE_MDIO */
1294 /* Set or clear the multicast filter for this adaptor.
1295 * Skeleton taken from sunlance driver.
1296 * The CPM Ethernet implementation allows Multicast as well as individual
1297 * MAC address filtering. Some of the drivers check to make sure it is
1298 * a group multicast address, and discard those that are not. I guess I
1299 * will do the same for now, but just remove the test if you want
1300 * individual filtering as well (do the upper net layers want or support
1301 * this kind of feature?).
1304 set_multicast_list(struct net_device *dev)
1306 struct fcc_enet_private *cep;
1307 struct dev_mc_list *dmi;
1308 u_char *mcptr, *tdptr;
1309 volatile fcc_enet_t *ep;
1312 cep = (struct fcc_enet_private *)dev->priv;
1315 /* Get pointer to FCC area in parameter RAM.
1317 ep = (fcc_enet_t *)dev->base_addr;
1319 if (dev->flags&IFF_PROMISC) {
1321 /* Log any net taps. */
1322 printk("%s: Promiscuous mode enabled.\n", dev->name);
1323 cep->fccp->fcc_fpsmr |= FCC_PSMR_PRO;
1326 cep->fccp->fcc_fpsmr &= ~FCC_PSMR_PRO;
1328 if (dev->flags & IFF_ALLMULTI) {
1329 /* Catch all multicast addresses, so set the
1330 * filter to all 1's.
1332 ep->fen_gaddrh = 0xffffffff;
1333 ep->fen_gaddrl = 0xffffffff;
1336 /* Clear filter and add the addresses in the list.
1343 for (i=0; i<dev->mc_count; i++) {
1345 /* Only support group multicast for now.
1347 if (!(dmi->dmi_addr[0] & 1))
1350 /* The address in dmi_addr is LSB first,
1351 * and taddr is MSB first. We have to
1352 * copy bytes MSB first from dmi_addr.
1354 mcptr = (u_char *)dmi->dmi_addr + 5;
1355 tdptr = (u_char *)&ep->fen_taddrh;
1357 *tdptr++ = *mcptr--;
1359 /* Ask CPM to run CRC and set bit in
1362 cpmp->cp_cpcr = mk_cr_cmd(cep->fip->fc_cpmpage,
1363 cep->fip->fc_cpmblock, 0x0c,
1364 CPM_CR_SET_GADDR) | CPM_CR_FLG;
1366 while (cpmp->cp_cpcr & CPM_CR_FLG);
1373 /* Set the individual MAC address.
1375 int fcc_enet_set_mac_address(struct net_device *dev, void *p)
1377 struct sockaddr *addr= (struct sockaddr *) p;
1378 struct fcc_enet_private *cep;
1379 volatile fcc_enet_t *ep;
1383 cep = (struct fcc_enet_private *)(dev->priv);
1386 if (netif_running(dev))
1389 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1391 eap = (unsigned char *) &(ep->fen_paddrh);
1392 for (i=5; i>=0; i--)
1393 *eap++ = addr->sa_data[i];
1399 /* Initialize the CPM Ethernet on FCC.
1401 int __init fec_enet_init(void)
1403 struct net_device *dev;
1404 struct fcc_enet_private *cep;
1407 volatile immap_t *immap;
1408 volatile iop8260_t *io;
1410 immap = (immap_t *)IMAP_ADDR; /* and to internal registers */
1411 io = &immap->im_ioport;
1413 np = sizeof(fcc_ports) / sizeof(fcc_info_t);
1418 /* Allocate some private information.
1420 cep = (struct fcc_enet_private *)
1421 kmalloc(sizeof(*cep), GFP_KERNEL);
1425 __clear_user(cep,sizeof(*cep));
1426 spin_lock_init(&cep->lock);
1429 /* Create an Ethernet device instance.
1431 dev = init_etherdev(0, 0);
1434 init_fcc_shutdown(fip, cep, immap);
1435 init_fcc_ioports(fip, io, immap);
1436 init_fcc_param(fip, dev, immap);
1438 dev->base_addr = (unsigned long)(cep->ep);
1440 /* The CPM Ethernet specific entries in the device
1443 dev->open = fcc_enet_open;
1444 dev->hard_start_xmit = fcc_enet_start_xmit;
1445 dev->tx_timeout = fcc_enet_timeout;
1446 dev->watchdog_timeo = TX_TIMEOUT;
1447 dev->stop = fcc_enet_close;
1448 dev->get_stats = fcc_enet_get_stats;
1449 dev->set_multicast_list = set_multicast_list;
1450 dev->set_mac_address = fcc_enet_set_mac_address;
1452 init_fcc_startup(fip, dev);
1454 printk("%s: FCC ENET Version 0.3, ", dev->name);
1456 printk("%02x:", dev->dev_addr[i]);
1457 printk("%02x\n", dev->dev_addr[5]);
1459 #ifdef CONFIG_USE_MDIO
1460 /* Queue up command to detect the PHY and initialize the
1461 * remainder of the interface.
1464 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
1465 #endif /* CONFIG_USE_MDIO */
1473 /* Make sure the device is shut down during initialization.
1476 init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
1477 volatile immap_t *immap)
1479 volatile fcc_enet_t *ep;
1480 volatile fcc_t *fccp;
1482 /* Get pointer to FCC area in parameter RAM.
1484 ep = (fcc_enet_t *)(&immap->im_dprambase[fip->fc_proff]);
1486 /* And another to the FCC register area.
1488 fccp = (volatile fcc_t *)(&immap->im_fcc[fip->fc_fccnum]);
1489 cep->fccp = fccp; /* Keep the pointers handy */
1492 /* Disable receive and transmit in case someone left it running.
1494 fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT);
1497 /* Initialize the I/O pins for the FCC Ethernet.
1500 init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
1501 volatile immap_t *immap)
1504 /* FCC1 pins are on port A/C. FCC2/3 are port B/C.
1506 if (fip->fc_proff == PROFF_FCC1) {
1507 /* Configure port A and C pins for FCC1 Ethernet.
1509 io->iop_pdira &= ~PA1_DIRA0;
1510 io->iop_pdira |= PA1_DIRA1;
1511 io->iop_psora &= ~PA1_PSORA0;
1512 io->iop_psora |= PA1_PSORA1;
1513 io->iop_ppara |= (PA1_DIRA0 | PA1_DIRA1);
1515 if (fip->fc_proff == PROFF_FCC2) {
1516 /* Configure port B and C pins for FCC Ethernet.
1518 io->iop_pdirb &= ~PB2_DIRB0;
1519 io->iop_pdirb |= PB2_DIRB1;
1520 io->iop_psorb &= ~PB2_PSORB0;
1521 io->iop_psorb |= PB2_PSORB1;
1522 io->iop_pparb |= (PB2_DIRB0 | PB2_DIRB1);
1524 if (fip->fc_proff == PROFF_FCC3) {
1525 /* Configure port B and C pins for FCC Ethernet.
1527 io->iop_pdirb &= ~PB3_DIRB0;
1528 io->iop_pdirb |= PB3_DIRB1;
1529 io->iop_psorb &= ~PB3_PSORB0;
1530 io->iop_psorb |= PB3_PSORB1;
1531 io->iop_pparb |= (PB3_DIRB0 | PB3_DIRB1);
1534 /* Port C has clocks......
1536 io->iop_psorc &= ~(fip->fc_trxclocks);
1537 io->iop_pdirc &= ~(fip->fc_trxclocks);
1538 io->iop_pparc |= fip->fc_trxclocks;
1540 #ifdef CONFIG_USE_MDIO
1541 /* ....and the MII serial clock/data.
1543 io->iop_pdatc |= (fip->fc_mdio | fip->fc_mdck);
1544 io->iop_podrc &= ~(fip->fc_mdio | fip->fc_mdck);
1545 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1546 io->iop_pparc &= ~(fip->fc_mdio | fip->fc_mdck);
1547 #endif /* CONFIG_USE_MDIO */
1549 /* Configure Serial Interface clock routing.
1550 * First, clear all FCC bits to zero,
1551 * then set the ones we want.
1553 immap->im_cpmux.cmx_fcr &= ~(fip->fc_clockmask);
1554 immap->im_cpmux.cmx_fcr |= fip->fc_clockroute;
1558 init_fcc_param(fcc_info_t *fip, struct net_device *dev,
1559 volatile immap_t *immap)
1562 unsigned long mem_addr;
1565 struct fcc_enet_private *cep;
1566 volatile fcc_enet_t *ep;
1567 volatile cbd_t *bdp;
1568 volatile cpm8260_t *cp;
1570 cep = (struct fcc_enet_private *)(dev->priv);
1576 /* Zero the whole thing.....I must have missed some individually.
1577 * It works when I do this.
1579 memset((char *)ep, 0, sizeof(fcc_enet_t));
1581 /* Allocate space for the buffer descriptors in the DP ram.
1582 * These are relative offsets in the DP ram address space.
1583 * Initialize base addresses for the buffer descriptors.
1586 /* I really want to do this, but for some reason it doesn't
1587 * work with the data cache enabled, so I allocate from the
1588 * main memory instead.
1590 i = m8260_cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
1591 ep->fen_genfcc.fcc_rbase = (uint)&immap->im_dprambase[i];
1592 cep->rx_bd_base = (cbd_t *)&immap->im_dprambase[i];
1594 i = m8260_cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
1595 ep->fen_genfcc.fcc_tbase = (uint)&immap->im_dprambase[i];
1596 cep->tx_bd_base = (cbd_t *)&immap->im_dprambase[i];
1598 cep->rx_bd_base = (cbd_t *)m8260_cpm_hostalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
1599 ep->fen_genfcc.fcc_rbase = __pa(cep->rx_bd_base);
1600 cep->tx_bd_base = (cbd_t *)m8260_cpm_hostalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
1601 ep->fen_genfcc.fcc_tbase = __pa(cep->tx_bd_base);
1604 cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;
1605 cep->cur_rx = cep->rx_bd_base;
1607 ep->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
1608 ep->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
1610 /* Set maximum bytes per receive buffer.
1611 * It must be a multiple of 32.
1613 ep->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
1615 /* Allocate space in the reserved FCC area of DPRAM for the
1616 * internal buffers. No one uses this space (yet), so we
1617 * can do this. Later, we will add resource management for
1620 mem_addr = CPM_FCC_SPECIAL_BASE + (fip->fc_fccnum * 128);
1621 ep->fen_genfcc.fcc_riptr = mem_addr;
1622 ep->fen_genfcc.fcc_tiptr = mem_addr+32;
1623 ep->fen_padptr = mem_addr+64;
1624 memset((char *)(&(immap->im_dprambase[(mem_addr+64)])), 0x88, 32);
1626 ep->fen_genfcc.fcc_rbptr = 0;
1627 ep->fen_genfcc.fcc_tbptr = 0;
1628 ep->fen_genfcc.fcc_rcrc = 0;
1629 ep->fen_genfcc.fcc_tcrc = 0;
1630 ep->fen_genfcc.fcc_res1 = 0;
1631 ep->fen_genfcc.fcc_res2 = 0;
1633 ep->fen_camptr = 0; /* CAM isn't used in this driver */
1635 /* Set CRC preset and mask.
1637 ep->fen_cmask = 0xdebb20e3;
1638 ep->fen_cpres = 0xffffffff;
1640 ep->fen_crcec = 0; /* CRC Error counter */
1641 ep->fen_alec = 0; /* alignment error counter */
1642 ep->fen_disfc = 0; /* discard frame counter */
1643 ep->fen_retlim = 15; /* Retry limit threshold */
1644 ep->fen_pper = 0; /* Normal persistence */
1646 /* Clear hash filter tables.
1653 /* Clear the Out-of-sequence TxBD.
1655 ep->fen_tfcstat = 0;
1659 ep->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
1660 ep->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
1662 /* Set Ethernet station address.
1664 * This is supplied in the board information structure, so we
1665 * copy that into the controller.
1666 * So, far we have only been given one Ethernet address. We make
1667 * it unique by toggling selected bits in the upper byte of the
1668 * non-static part of the address (for the second and third ports,
1669 * the first port uses the address supplied as is).
1671 eap = (unsigned char *)&(ep->fen_paddrh);
1672 for (i=5; i>=0; i--) {
1673 if (i == 3 && fip->fc_fccnum != 0) {
1674 dev->dev_addr[i] = bd->bi_enetaddr[i];
1675 dev->dev_addr[i] ^= (1 << (7 - fip->fc_fccnum));
1676 *eap++ = dev->dev_addr[i];
1679 *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];
1687 ep->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
1688 ep->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
1690 /* Clear stat counters, in case we ever enable RMON.
1707 ep->fen_rfthr = 0; /* Suggested by manual */
1711 /* Now allocate the host memory pages and initialize the
1712 * buffer descriptors.
1714 bdp = cep->tx_bd_base;
1715 for (i=0; i<TX_RING_SIZE; i++) {
1717 /* Initialize the BD for every fragment in the page.
1720 bdp->cbd_datlen = 0;
1721 bdp->cbd_bufaddr = 0;
1725 /* Set the last buffer to wrap.
1728 bdp->cbd_sc |= BD_SC_WRAP;
1730 bdp = cep->rx_bd_base;
1731 for (i=0; i<FCC_ENET_RX_PAGES; i++) {
1735 mem_addr = __get_free_page(GFP_KERNEL);
1737 /* Initialize the BD for every fragment in the page.
1739 for (j=0; j<FCC_ENET_RX_FRPPG; j++) {
1740 bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR;
1741 bdp->cbd_datlen = 0;
1742 bdp->cbd_bufaddr = __pa(mem_addr);
1743 mem_addr += FCC_ENET_RX_FRSIZE;
1748 /* Set the last buffer to wrap.
1751 bdp->cbd_sc |= BD_SC_WRAP;
1753 /* Let's re-initialize the channel now. We have to do it later
1754 * than the manual describes because we have just now finished
1755 * the BD initialization.
1757 cp->cp_cpcr = mk_cr_cmd(fip->fc_cpmpage, fip->fc_cpmblock, 0x0c,
1758 CPM_CR_INIT_TRX) | CPM_CR_FLG;
1759 while (cp->cp_cpcr & CPM_CR_FLG);
1761 cep->skb_cur = cep->skb_dirty = 0;
1767 init_fcc_startup(fcc_info_t *fip, struct net_device *dev)
1769 volatile fcc_t *fccp;
1770 struct fcc_enet_private *cep;
1772 cep = (struct fcc_enet_private *)(dev->priv);
1775 fccp->fcc_fcce = 0xffff; /* Clear any pending events */
1777 /* Enable interrupts for transmit error, complete frame
1778 * received, and any transmit buffer we have also set the
1781 fccp->fcc_fccm = (FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
1783 /* Install our interrupt handler.
1785 if (request_8xxirq(fip->fc_interrupt, fcc_enet_interrupt, 0,
1787 printk("Can't get FCC IRQ %d\n", fip->fc_interrupt);
1789 #ifdef CONFIG_USE_MDIO
1790 if (request_8xxirq(PHY_INTERRUPT, mii_link_interrupt, 0,
1792 printk("Can't get MII IRQ %d\n", fip->fc_interrupt);
1793 #endif /* CONFIG_USE_MDIO */
1795 /* Set GFMR to enable Ethernet operating mode.
1797 fccp->fcc_gfmr = (FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
1799 /* Set sync/delimiters.
1801 fccp->fcc_fdsr = 0xd555;
1803 /* Set protocol specific processing mode for Ethernet.
1804 * This has to be adjusted for Full Duplex operation after we can
1805 * determine how to detect that.
1807 fccp->fcc_fpsmr = FCC_PSMR_ENCRC;
1809 #ifdef CONFIG_ADS8260
1812 ads_csr_addr[1] |= BCSR1_FETH_RST; /* Remove reset */
1813 ads_csr_addr[1] &= ~BCSR1_FETHIEN; /* Enable */
1816 #if defined(CONFIG_USE_MDIO) || defined(CONFIG_TQM8260)
1817 /* start in full duplex mode, and negotiate speed
1819 fcc_restart (dev, 1);
1821 /* start in half duplex mode
1823 fcc_restart (dev, 0);
1827 #ifdef CONFIG_USE_MDIO
1828 /* MII command/status interface.
1829 * I'm not going to describe all of the details. You can find the
1830 * protocol definition in many other places, including the data sheet
1831 * of most PHY parts.
1832 * I wonder what "they" were thinking (maybe weren't) when they leave
1833 * the I2C in the CPM but I have to toggle these bits......
1836 #define FCC_PDATC_MDIO(bit) \
1838 io->iop_pdatc |= fip->fc_mdio; \
1840 io->iop_pdatc &= ~fip->fc_mdio;
1842 #define FCC_PDATC_MDC(bit) \
1844 io->iop_pdatc |= fip->fc_mdck; \
1846 io->iop_pdatc &= ~fip->fc_mdck;
1849 mii_send_receive(fcc_info_t *fip, uint cmd)
1852 int read_op, i, off;
1853 volatile immap_t *immap;
1854 volatile iop8260_t *io;
1856 immap = (immap_t *)IMAP_ADDR;
1857 io = &immap->im_ioport;
1859 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1861 read_op = ((cmd & 0xf0000000) == 0x60000000);
1865 for (i = 0; i < 32; i++)
1876 for (i = 0, off = 31; i < (read_op ? 14 : 32); i++, --off)
1879 FCC_PDATC_MDIO((cmd >> off) & 0x00000001);
1892 io->iop_pdirc &= ~fip->fc_mdio;
1899 for (i = 0, off = 15; i < 16; i++, off--)
1903 if (io->iop_pdatc & fip->fc_mdio)
1911 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1913 for (i = 0; i < 32; i++)
1926 fcc_stop(struct net_device *dev)
1928 volatile fcc_t *fccp;
1929 struct fcc_enet_private *fcp;
1931 fcp = (struct fcc_enet_private *)(dev->priv);
1934 /* Disable transmit/receive */
1935 fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT);
1937 #endif /* CONFIG_USE_MDIO */
1940 fcc_restart(struct net_device *dev, int duplex)
1942 volatile fcc_t *fccp;
1943 struct fcc_enet_private *fcp;
1945 fcp = (struct fcc_enet_private *)(dev->priv);
1949 fccp->fcc_fpsmr |= FCC_PSMR_FDE;
1951 fccp->fcc_fpsmr &= ~FCC_PSMR_FDE;
1953 /* Enable transmit/receive */
1954 fccp->fcc_gfmr |= FCC_GFMR_ENR | FCC_GFMR_ENT;
1958 fcc_enet_open(struct net_device *dev)
1960 struct fcc_enet_private *fep = dev->priv;
1962 #ifdef CONFIG_USE_MDIO
1963 fep->sequence_done = 0;
1967 mii_do_cmd(dev, fep->phy->ack_int);
1968 mii_do_cmd(dev, fep->phy->config);
1969 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1970 while(!fep->sequence_done)
1973 mii_do_cmd(dev, fep->phy->startup);
1974 netif_start_queue(dev);
1975 return 0; /* Success */
1977 return -ENODEV; /* No PHY we understand */
1980 netif_start_queue(dev);
1981 return 0; /* Always succeed */
1982 #endif /* CONFIG_USE_MDIO */